대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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- Pages.160-163
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- 2000
고속 다이나믹 래치 비교기의 오프셋 최소화 기법
An Offset Reduction Technique of High Speed Dynamic latch comparator
초록
In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65
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