상보형 패스 트랜지스터를 이용한 저전력, 고속력 Delay Locked-Loop 설계

Low-power, fast-locking All Digital Delay Locked-loop Using Complementary Pass-Transistor Logic

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.