대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2000년도 ITC-CSCC -2
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- Pages.1084-1087
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- 2000
Simulated Annealing Approach to Evaluation of Maximum Number of Simultaneous Switching Gates
- Seko, Tadashi (Nara National College of Technology) ;
- Ohara, Makoto (Nara National College of Technology) ;
- Kikuno, Tohru (Graduate School of Engineering Science, Osaka University)
- 발행 : 2000.07.01
초록
This paper presents a new approach to evaluate the maximum number of simultaneous switching gates of a given combinational circuit. The new approach is based on an iterative method proposed by Sinogi et al. and applies a simulated annealing strategy to search jot a new solution. The experimental evaluation using ISCAS’85 benchmark circuits shows that the proposed approach has attained an excellent improvement compared with other rotated methods including the iterative method.
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