Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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The relationship between addressing time and dielectric layer, barrier rib hight

AC PDP의 addressing time과 유전체 및 Barrier Rib 높이와의 상관관계

  • Park, J.T. (Pusan National University, Dept. of Electrical Eng.) ;
  • Park, C.S. (Pusan National University, Dept. of Electrical Eng.) ;
  • Song, K.D. (Pusan National University, Dept. of Electrical Eng.) ;
  • Park, C.H. (Pusan National University, Dept. of Electrical Eng.) ;
  • Cho, J.S. (Pusan National University, Dept. of Electrical Eng.)
  • Published : 2000.07.17
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Abstract

Up to date, the dual scanning method has been adopted to decrease address-ing period in AC PDP. In this case, addressing period can be reduced, but the driving circuit cost should be increased. In this study, to increase addressing speed we have studied the relationship between addressing speed and cell structure. That is to say, we varied the thickness of dielectric layer on the front glass, the thickness of white back and the height of barrier rib on the rear glass. So, we found that the addressing time was decreased 4% with decreasing 5um thickness of dielectric layer on the front glass and 2um thickness of white back on the rear glass. Also in case of decreasing the height of barrier rib, addressing time was decreased about 4% per 10um.

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