Design of a Low Power 108-bit Conditional Sum Adder Using Energy Economized Pass-transistor Logic(EEPL)

EEPL을 사용한 저 전력 108-bit 조건합 가산기의 설계

In this paper, a novel 108-bit conditional sum adder(CSA) with Energy Economized Pass-transistor Logic(EEPL) is proposed. A new architecture is adopted, in order to obtain a high speed operation, which is composed of seven modularized 16-bit CMS's and two separated carry generation block. Further a design technique based on EEPL is proposed to reduce the power consumption. With 0.65${\mu}{\textrm}{m}$ single poly, triple metal, 3.3V CMOS process, its operating speed is about 4.95㎱ and the power consumption is reduced in comparison with that of the conventional adder.