대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1999년도 추계종합학술대회 논문집
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- Pages.275-278
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- 1999
위상동기시간을 개선한 Dual PFD 설계
Design of Dual PFD with Improved Phase Locking Time
초록
In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25
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