대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1999년도 추계종합학술대회 논문집
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- Pages.255-258
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- 1999
투스텝 구조를 가진 10비트 40Msample/s 폴딩&인터폴레이팅 아날로그-디지털 변환기
A 10-bit 40-Msample/s Folding & Interpolating A/D Converter with two-step Architecture
초록
This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25
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