A 10-bit 40-Msample/s Folding & Interpolating A/D Converter with two-step Architecture

투스텝 구조를 가진 10비트 40Msample/s 폴딩&인터폴레이팅 아날로그-디지털 변환기

  • 김수환 (고려대학교 전자공학과) ;
  • 성준제 (고려대학교 전자공학과) ;
  • 김태형 (고려대학교 전자공학과) ;
  • 김석기 (고려대학교 전자공학과) ;
  • 임신일 (서경대학교 컴퓨터공학과)
  • Published : 1999.11.01

Abstract

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

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