Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Characteristics of the Novel Gate Insulator Structured Poly-Si TFT's

새로운 게이트 절연막 구조를 가지는 다결정 실리콘 박막 트랜지스터

  • Hwang, Han-Wook (Dep't of Electrical Engineering, Myongji University) ;
  • Choi, Yong-Won (Dep't of Electrical Engineering, Myongji University) ;
  • Kim, Yong-Sang (Dep't of Electrical Engineering, Myongji University) ;
  • Kim, Han-Soo (Dep't of Electrical Engineering, Doowon Technical College)
  • Published : 1999.07.19
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Abstract

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.

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