대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

고 전압 FED용 Spacer형성 기술 개발

Development of spacer formation techni4ue for high-voltage FED application

  • 강문식 (한국과학기술연구원 정보재료.소자연구센터) ;
  • 주병권 (한국과학기술연구원 정보재료.소자연구센터) ;
  • 이윤희 (한국과학기술연구원 정보재료.소자연구센터) ;
  • 유건호 (경희대학교 물리학과) ;
  • 오명환 (한국과학기술연구원 정보재료.소자연구센터)
  • Kang, M.S. (Electronic Materials and Device Research Center, KIST) ;
  • Ju, B.K. (Electronic Materials and Device Research Center, KIST) ;
  • Lee, Y.H. (Electronic Materials and Device Research Center, KIST) ;
  • Yu, K.H. (Department of Physics, Kyung-hee univ) ;
  • Oh, M.H. (Electronic Materials and Device Research Center, KIST)
  • 발행 : 1999.07.19
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초록

This paper presents a new method of spacer assembly using anodic bonding method which is very simple and clean. The spacer having $100{\mu}m(W){\times}2.1{\mu}m(H)$ was bonded on amorphous silicon film of anode plate. Then, the vertical-type electrode was used for assembling of spacer in high voltage field emission display. In these results, we suggested that the vertical-type electrode provided spacer alignment for high aspect ratio and more simple batch process than conventional method.

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