FPGA Implementation of PN Code Searcher with a Shared Architecture for CDMA PCS mobile Station

공유구조를 가지는 CDMA 이동국용 PN 부호 탐색기의 FPGA 구현

In this paper, we propose a new architecture of the PN code acquistion system which has some shared blocks in order to reduce the hardware complexity. The proposed system has an energy calculation block which is shared by two active correlators. Our system is designed suitable for IS-95 based CDMA PCS. The new architecture was designed and simulated using VHDL. Also, We implemented it with Altera FPGA, and verified our system. The gate count is about 7,500. Our proposed architecture is also useful for multi-carrier system which uses the multiple searcher.