Design of A 3.3V, 400 MBPS IEEE-1394 Physical Layer Transceiver

3.3V, 400MBPS IEEE-1394 물리층 트랜시버의 설계

We designed a 3.3 V, 400 Mbps IEEE-1394 physical layer transeiver on 0.6um 1P3M CMOS process. The transceiver drives a twisted pair cable of which differential impedance is 110 $\Omega$ so that differential amplitude reaches 200 mV at 400 Mbps and restores this small signal to rail-to-rail. Also, the transceiver arbitrates the interface among nodes on a bus configuration and supports both synchronous interface and asynchronous interface.