Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 1998.10a
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- Pages.763-766
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- 1998
Design of the Integer Processor Unit for RAPTOR
Raptor의 정수처리기 설계
Abstract
This paper describes the microarchitecture of the integer processor unit of RAPTOR which is an on-chip multiprocessor. The integer processor unit implements the 64-bit SPARC-V9 architecture and supports by hardware out-of-order instruction execution. The unit is designed to be handy so that multiple copies of the unit cn be integrated with cache memories into a single chip. The design was proceeded in a top-down manner. The hardware description and its verfication were performed using Verilog-HDL.
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