전력전자학회:학술대회논문집 (Proceedings of the KIPE Conference)
- 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
- /
- Pages.518-523
- /
- 1998
A NOBLE DEAD TIME MINIMIZATION ALGORITHM FOR REDUCING THE INVERTER SWITCHING LOSSES
- Choi, Jung-Soo (School of Electrical & Computer Engineering, Inha University) ;
- Han, Yoon-seok (School of Electrical & Computer Engineering, Inha University) ;
- Kim, Young-seok (School of Electrical & Computer Engineering, Inha University)
- 발행 : 1998.10.01
초록
In this paper, a noble dead time minimization algorithm is presented for developing the outputs of inverters. The adverse effects of the dead time are examined. The principle of the proposed algorithm is explained with the conduction modes of the output currents. The H/W and the S/W construction method of the proposed algorithm are also presented. The validity of the proposed algorithm is verified by comparing simulation and experimental results with those of the conventional methods. It can be concluded from the results that the proposed algorithm have the virtue which is able to ruduce the numbers of inverter switching and the harmonics in the output voltages, and which make the output voltage equal to the reference value.
키워드