Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1998.07d
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- Pages.1361-1363
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- 1998
Analysis of Grain Boundary Effects in Poly-Si Wafer for the Fabrication of Low Cost and High Efficiency Solar Cells
저가 고효율 태양전지 제작을 위한 다결정 실리콘 웨이퍼 결정입계 영향 분석
- Lee, S.E. (ECE Sung Kyun Kwan University) ;
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Lim, D.G.
(ECE Sung Kyun Kwan University) ;
- Kim, H.W. (KERI) ;
- Kim, S.S. (Samsung Electronics Co. Ltd.) ;
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Yi, J.
(ECE Sung Kyun Kwan University)
- 이수은 (성균관대학교 전기 전자 및 컴퓨터공학부) ;
-
임동건
(성균관대학교 전기 전자 및 컴퓨터공학부) ;
- 김홍우 (한국에너지기술연구소) ;
- 김상수 (삼성전자) ;
-
이준신
(성균관대학교 전기 전자 및 컴퓨터공학부)
- Published : 1998.07.20
Abstract
Poly-Si grain boundaries act as potential barriers as well as recombination centers for the photo-generated carriers in solar cells. Thereby, grain boundaries of poly-Si are considered as a major source of the poly-Si cell efficiency was reduced This paper investigated grain boundary effect of poly-Si wafer prior to the solar cell fabrication. By comparing I-V characteristics inner grain, on and across the grain boundary, we were able to detect grain potentials. To reduce grain boundary effect we carried out pretreatment,
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