Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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Structure Optimization of Inverted-Staggered a-Si TFT Using a Two-Dimensional Device Simulator

이차원 소자 시뮬레이터를 이용한 역 스태거형 비정질 실리콘 박막 트랜지스터의 구조 최적화

  • Kwak, Ji-Hoon (School of Electronic and Electrical Engineering, Hongik University) ;
  • Choi, Jong-Sun (School of Electronic and Electrical Engineering, Hongik University)
  • 곽지훈 (홍익대학교 전자전기공학부) ;
  • 최종선 (홍익대학교 전자전기공학부)
  • Published : 1997.07.21
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Abstract

TFT2DS was utilized to provide the usefulness as an analytic and design tool. In this paper, the general effects of channel length of an inverted staggered amorphous silicon thin film transistor on its characteristics were investigated. The results obtained from these experiments would be adopted to the optimized device designs and advanced simulations of their electrical properties.

Keywords