UPS용 위상동기화기법의 특성개선

Characteristic Improvement of Phase-Locked Technique for UPS

  • 김제홍 (충북대학교 공과대학 전기공학과) ;
  • 김병진 (충북대학교 공과대학 전기공학과) ;
  • 정영석 (충북대학교 공과대학 전기공학과) ;
  • 곽주식 (충북대학교 공과대학 전기공학과) ;
  • 최재호 (충북대학교 공과대학 전기공학과)
  • Kim, J.H. (Dept. of Electrical Eng., Chungbuk National University) ;
  • Kim, B.J. (Dept. of Electrical Eng., Chungbuk National University) ;
  • Jung, Y.S. (Dept. of Electrical Eng., Chungbuk National University) ;
  • Kwak, J.S. (Dept. of Electrical Eng., Chungbuk National University) ;
  • Choi, J.H. (Dept. of Electrical Eng., Chungbuk National University)
  • 발행 : 1995.07.20

초록

An UPS must be synchronized in frequency and phase relationship with the mains power supply. This paper describes and tests a digital phase-locked loop(DPLL) circuit of the open-loop method designed by full software with TMS320c31 digital signal processor. finally, the performance of the proposed DPLL is shown and discussed through simulation and experiment.

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