Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

The Optimal Design of Inverter Planar Bus Structure for Reducing the Stray inductance

스트레이 인덕턴스 저감(低減)을 위한 인버터 평판 부스의 형상 최적 설계

  • Roh, Ji-Joon (Dept. of Electrical Engineering, Seoul National University) ;
  • Sul, Seung-Ki (Dept. of Electrical Engineering, Seoul National University)
  • 노지준 (서울대학교 공과대학 전기공학과) ;
  • 설승기 (서울대학교 공과대학 전기공학과)
  • Published : 1994.11.18
Download PDF
⟨ Previous Next ⟩

Abstract

In recent days, the inverter is widely used at the industrial applications. In the range lower than 100[kW], IGBT(Insulated Gate Bipolar Transistor) is most widely used as the switching device. In that case of IGBT, the rising time and the filling time are very short(about $200[ns]{\sim}300[ns]$). Especially for motor control applications, the switching frequency is required to be increased for better dynamic performance of the drive. However, the higher switching frequency leads to the unexpected problem occurs such as voltage spike due to stray inductance in the bus at switching instant. In this paper, a new methodology for reducing the stray inductance existing in the bus that induces the voltage spike will be presented.

Keywords