Simulation of optimal ion implantation for symmetric threshold voltage determination of 1 ${\mu}m$ CMOS device

1 ${\mu}m$ CMOS 소자의 대칭적인 문턱전압 결정을 위한 최적 이온주입 시뮬레이션

We simulated ion implantation and annealing condition of 1 ${\mu}m$ CMOS device using process simulator, SUPREM-II. In this simulation, optimal condition of ion implantation for symmetric threshold voltage determination of PMOS and NMOS region, junction depth and sheet resistance of source/drain region, impurity profile of each region are investigated. Ion implantation dose for 3 ${\mu}m$ N-well junction depth and symmetric threshold voltage of $|0.6|{\pm}0.1$ V were $1.9E12Cm^{-2}$(for phosphorus), $1.7E122Cm^{-2}$(for boron) respectively. Also annealing condition for dopant activation are examined about $900^{\circ}C$, 30 minutes. After final process step, N-well junction, P+ S/D junction and N+ S/D junction depth are calculated 3.16 ${\mu}m$, 0.45 ${\mu}m$ and 0.25 ${\mu}m$ respectively.