Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

Transputer-based Pyramidal Parallel Array Computer(TPPAC) architecture (Prelimineary Version)

트랜스퓨터를 사용한 피라미드형 병렬 어레이 컴퓨터 (TPPAC) 구조

  • Jeong, Chang-Sung (High Performance Computer Lab., Dept. of Computer Science Pohang Institute of Science and Technology) ;
  • Jeong, Chul-Hwan (High Performance Computer Lab., Dept. of Computer Science Pohang Institute of Science and Technology)
  • 정창성 (포항 공과 대학 전자계산학과 고성능 컴퓨터 연구실) ;
  • 정철환 (포항 공과 대학 전자계산학과 고성능 컴퓨터 연구실)
  • Published : 1988.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

Keywords