A CMOS Gate Array Global Router which regards Macrocell and I/O padcell

Macro셀과 I/O pad셀을 고려한 CMOS 게이트 어레이 Global Router

For CMOS, this paper propose a new global routing algorithm in which macrocells and I/O padcells can be treated. Not only predefined feedthrough in base array, but also some polysilicon line which are not assigned as inputs are used to prevent the overflow of nets passing through the row. The signal nets are assigned on their feedthrough by the maze router. By treating macrocells and I/O padcell, the routing from internal to I/O cell can be done automatically and a kind of is constraints in design process can be reduced.