Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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An Implementation of parallel Decoder for TEC-BCH codes

3중 오류정정 BCH부호의 병렬복호기 구현에 관한연구

  • 김창수 (한양대학교 대학원 전자통신공학과) ;
  • 이만영 (한양대학교 대학원 전자통신공학과)
  • Published : 1988.07.01
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Abstract

Some efficient methods for solving the equations over GF($2^m$) are proposed in this paper. Using these algorithms, parallel decoder for a triple-error-correcting(31, 16) BCH code is implemented. By incorporating with ROM and PAL which are inserted in a decoder, the complex logic circuits can be substantially reduced and therefore a high speed decoder can be constructed.

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