대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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- Pages.14-16
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- 1988
Systolic Array Processor Architecture를 이용한 Discrete Hartley Transform 의 병렬 처리 실행
Parallel Processing Implementation of Discrete Hartley Transform using Systolic Array Processor Architecture
- Kang, J.K. (Dept. of Electronics Engineering Chung-Ang University) ;
- Joo, C.H. (Dept. of Electronics Engineering Chung-Ang University) ;
- Choi, J.S. (Dept. of Electronics Engineering Chung-Ang University)
- 발행 : 1988.07.01
초록
With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.
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