Dual-Digital Phase-Locked Loop에 관한 연구

A study on the Dual Digital Phase Locked Loop

  • 김수일 (숭실대학교 전자공학과) ;
  • 이상범 (숭실대학교 전자공학과) ;
  • 성상기 (숭실대학교 전자공학과) ;
  • 김중태 (숭실대학교 전자공학과) ;
  • 최승철 (숭실대학교 전자공학과)
  • 발행 : 1987.04.01

초록

A Dual Disital Phase Locked Loop is analyzeddesigned and tested. Two specific confisurations are considered generations second and thisrd order DPLL’s and it is found using a computer simulation and verified therretically . As a result of computer simulation the characteristcof designed I-Dullis better than the at of P-DPLL or C-Dull

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