Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1987.07b
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- Pages.1560-1563
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- 1987
Delay time modeling for E/D MOS Logic LSI.
E/D MOS 논리 LSI의 지연시간 모델링
- Jun, Ki (Dept. of E.E. KAIST) ;
- Kim, Kyung-Ho (Dept. of E.E. KAIST) ;
- Jun, Young-Hyun (Dept. of E.E. KAIST) ;
- Park, Song-Bai (Dept. of E.E. KAIST)
- 전기 (한국 과학기술원 전기 및 전자공학과) ;
- 김경호 (한국 과학기술원 전기 및 전자공학과) ;
- 전영현 (한국 과학기술원 전기 및 전자공학과) ;
- 박송배 (한국 과학기술원 전기 및 전자공학과)
- Published : 1987.07.03
Abstract
This paper is concerned with time delay modeling of ED MOS gates which takes into account the slope of input waveform as well as the load condition. Defining the delay time as the time required to charge/discharge the load to the physical reference level, the rise/fall delay times arc derived in an explicit formula in terms of the sum of optimally weighted current unbalances at two end points of voltage transition. The proposed model is computationally effective and the error is typically within 10% of the SPICE results.
Keywords