Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

KUIC-CEX: Circuit EXtraction from IC mask pattern of the CMOS

KUIC-CEX: 집적회로 마스크 도면으로 부터의 회로 추출

  • Bae, Yun-Seob (Dept. of Electronics, Kyungpook National University.) ;
  • Jang, Gi-Dong (Dept. of Electronics, Kyungpook National University.) ;
  • Seo, In-Hwan (Dept. of Electronics, Kyungpook National University.) ;
  • Jeong, Gab-Jung (Dept. of Electronics, Kyungpook National University.) ;
  • Chung, Ho-Sun (Dept. of Electronics, Kyungpook National University.) ;
  • Lee, Wu-Il (Dept. of Electronics, Kyungpook National University.)
  • 배윤섭 (경북 대학교 전자 공학과) ;
  • 장기동 (경북 대학교 전자 공학과) ;
  • 서인환 (경북 대학교 전자 공학과) ;
  • 정갑중 (경북 대학교 전자 공학과) ;
  • 정호선 (경북 대학교 전자 공학과) ;
  • 이우일 (경북 대학교 전자 공학과)
  • Published : 1987.07.03
Download PDF
⟨ Previous Next ⟩

Abstract

This paper describe the KUIC-CEX, an automated CMOS layout verification program which extracts circuit connectivity, MOSFET dimensions, and parasitic capacitance for CIF(1) file. In the KUIC-CEX, Bitmap approach(2, 3) is used for basic operation. Since the output of this program is the Input file format of PSPICE, we can easily verify the layout of circuit. This program is written in C language.

Keywords