테스트가 용이한 순서 NMOS PLA의 설계

Testable Design of Sequential NMOS PLAs

This paper proposes testable design of sequential NMOS PLAs. The extra bit lines and devices are added to the conventional PLAs. The time is taken to assigning devices in the extra bit lines, which is excessive in the conventional method, is reduced by using the symmetrical distance matrix of the PLA and the regular assigning method. As a result, the test patterns can be easily generated. Also, the silicon area overhead of extra hardware is low.