Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1987.07b
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- Pages.874-877
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- 1987
Detection of FSK and Bit error rate using a first-order Digital PLL
1차 Digital PLL을 이용한 FSK 복조 및 BIT ERROR RATE 측정
- Chung, Hyun-Gi (Dept. of electronic eng. Soongsil University) ;
- Park, Ju-Ho (Dept. of electronic eng. Soongsil University) ;
- Joo, Jung-Kyu (Dept. of electronic eng. Soongsil University) ;
- Shim, Soo-Bo (Dept. of electronic eng. Soongsil University)
- Published : 1987.07.03
Abstract
In this paper a DPLL circuit realizable by digital IC's is propose and the principles of general DPLL are described. An all Digital phase locked loop is designed, analyzed, and tested. In particular, the approach of invoking Gaussian assumption on the decision variable and based on S.O.Rices theory is used. As a performance of the above PLL detector operating on low data rate FSK is given and demonsrtated to be FSK reception.
Keywords