• 제목/요약/키워드: zero suppression

검색결과 54건 처리시간 0.024초

단전원 듀얼 인버터의 데드타임으로 인한 영상전류 억제 방법 (Suppression of Zero Sequence Current Caused by Dead-time for Dual Inverter With Single Source)

  • 윤범렬;김태형;이준희;이준석
    • 전력전자학회논문지
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    • 제27권2호
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    • pp.126-133
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    • 2022
  • This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.

Zero Suppression 알고리듬들의 여러 가치 특성 비교 (Comparisons of Various Properties for Zero Suppression Algorithms)

  • 이훈재;박영호
    • 한국산업정보학회논문지
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    • 제6권1호
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    • pp.7-14
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    • 2001
  • 동기식 스트림 암호 시스템 적용을 위한 ZS 동기 알고리듬이 다수 제안된 바 있지만, 그 중에서 ZS-1 알고리듬은 스트림 암호 시스템 구현상의 어려움이 있고, ZS-2 알고리듬은 에러 확산이 많으며, ZS-3는 회로가 복잡해지는 단점을 갖는다. 그리고 이들 알고리듬은 적용 분야를 주의하여 선택하여야 할 필요성이 있으며, 본 논문에서는 몇 가지 파라메터 변화에 따른 결과 값의 비교를 통하여 주어진 시스템에 적합한 알고리듬을 선택하는 방향을 제시하였다.

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Model Predictive Control of Circulating Current Suppression in Parallel-Connected Inverter-fed Motor Drive Systems

  • Kang, Shin-Won;Soh, Jae-Hwan;Kim, Rae-Young
    • Journal of Electrical Engineering and Technology
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    • 제13권3호
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    • pp.1241-1250
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    • 2018
  • Parallel three-phase voltage source inverters in a direct connection configuration are widely used to increase system power ratings. A zero-sequence circulating current can be generated according to the switching method; however, the zero-sequence circulating current not only distorts current, but also reduces the system reliability and efficiency. In this paper, a model predictive control scheme is proposed for parallel inverters to drive an interior permanent magnet synchronous motor with zero-sequence circulating current suppression. The voltage vector of the parallel inverters is derived to predict and control the torque and stator flux components. In addition, the zero-sequence circulating current is suppressed by designing the cost function without an additional current sensor and high-impedance inductor. Simulation and experimental results are presented to verify the proposed control scheme.

병렬 3레벨 AC/DC 전력변환 시스템의 영상분 순환전류 억제 (Suppression of Circulating Current in Parallel Operation of Three-Level AC/DC Converters)

  • 손영광;지승준;이영기;설승기
    • 전력전자학회논문지
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    • 제21권4호
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    • pp.312-319
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    • 2016
  • Zero-sequence Circulating Current (ZSCC) flows inevitably in parallel converters that share common DC and AC sources. The ZSCC commonly flowing in all converters increases loss and decreases the overall capacity of parallel converters. This paper proposes a simple and effective ZSCC suppression method based on the Space Vector PWM (SVPWM) with the ZSCC controller. The zero-sequence voltage for the proposed SVPWM is calculated on the basis of the grid voltage and not on the phase voltage references. The limit of the linear modulation region of the converters with the proposed method is analyzed and compared with other methods, thereby proving that the limit of the region can be extended with the proposed method. The effectiveness of the proposed method has been verified through the experimental setup comprising four parallel three-level converters. The ZSCC is confirmed to be well suppressed, and the linear modulation region is extended simultaneously with the proposed method. Moreover, the proposed control method does not require any communication between the converters to suppress the ZSCC unlike other conventional methods.

고속 동기식 스트림 암호에서의 ZS 동기 방식 개선 (An Improved ZS Algorithm for High-Speed Synchronous Stream Ciphers)

  • 이훈재
    • 정보처리학회논문지C
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    • 제9C권3호
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    • pp.307-312
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    • 2002
  • 동기식 스트림 암호에 적용하기 위한 여러 가지 Zero suppression(ZS) 알고리즘 중에서 ZS-2 알고리즘은 블록동기기능 제거, 구현 용이성 등 여러 가지 좋은 특성을 보여주고 있다. 하지만, 이 방법은 채널 오류 확산 측면에서 취약점을 보이고 있다. 따라서, 본 논문에서는 열악한 잡음 채널에서 오류 확률에 따른 성능을 개선하기 위하여 ZS-2에서 실행했던 대체 블록에서의 대체 비트 수를 최소화시키는 새로운 방법을 제안하였다. 결과적으로, 제안된 ZS-3 기법은 n=8에서 평균 오류 확산을 ZS-2의 값 보다 18.7% 떨어뜨리는 좋은 특성을 나타냄을 확인하였다.

공진소멸 현상을 이용한 기존선 철도교량의 지간 최적화를 위한 연구 (A Study on the Optimal Span Length Selection of Conventional Railway Bridges considering Resonance Suppression)

  • 김성일;정원석;최은수
    • 한국철도학회논문집
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    • 제8권2호
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    • pp.137-144
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    • 2005
  • The possibility of resonance exists always in railway bridges unlike highway bridges because railway bridges are loaded repeatedly by specific trains which has equidistant wheel loads. Resonance phenomenon of the bridge can be broken out when exciting frequencies by tram determined from the speed and effective beating internal coincides with natural frequencies of the bridge Excessive fluctuations of dynamic displacements and accelerations by resonance cause unpleasant passenger comfort and instability of railway structures. On the other hand, resonance suppression phenomenon that all the previous loads which pass through the bridge sum to zero can be occurred. In case we apply this resonance suppression properly, design of stable railway bridge from dynamics point of view can be made. In the present study, most dominant beating internal of conventional trams will be find. A(ter that. specific span length of the bridge which derives resonance suppression can be selected for railway bridges which accomplishes superior dynamic behavior.

Spin injection and transport properties of Co/Au/Y$Ba_2$$Cu_3$$O_y$ tunnel junctions

  • Lee, Kiejin;Kim, Sunmi;Ishibashi, Takauki;Cha, Deokjoon
    • Progress in Superconductivity
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    • 제3권1호
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    • pp.70-73
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    • 2001
  • We report the spin injection and transport properties of three terminal devices of Co/Au/$YBa_2$$Cu_3$$O_{y}$(F/N/S) tunnel junctions by injection of spin-polarized quaiparticles using a cobalt ferromagnetic injector. The observed current gain depends on the thickness of Au interlayer and is directly related to the nonequilibrium magnetization due to spin relaxation effects. The tunnel characteristic of a F/N/S tunnel junctions exhibited a zero bias conductance peak (ZBCP). The suppression of the ZBCP was observed due to the suppression of Andreev reflection at the interface, which is due to the spin scattering processes at the interface between a ferromagnetic and a d-wave superconductor.r.

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Space vector modulation을 이용한 대용량 멀티 레벨 H-bridge 인버터의 해석 및 모델링 (Analysis and modelling of the large capacity multilevel H-bridge inverter using Space vector modulation)

  • 김효진;정승기
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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    • pp.5-9
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    • 2003
  • Conventional variable-speed Induction motor drives with inverters are subject to detrimental effect of zero-sequence voltages, such a shaft voltage and bearing current. This paper presents a way of the suppression of the zero-sequence components in multilevel H-bridge inverters. First examined Is the inherent zero-sequence characteristic of the conventional subharmonic PW method. Then it is shown that the zero-sequence voltage can be eliminated with proper -selection of switching states with space vector modulation. Although this method alone restricts the linear modulation range of control, a combination of the proposed method and the minimum switching method appears to be effective in suppressing the zero-sequence voltage to minimum level while maintaining the linear control range.

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유연 OLED 디스플레이의 기계적 안정성을 위한 제로 스트레스 봉지막 설계 (Design of Zero-Stress Encapsulation for Mechanical Stability of Flexible OLED Displays)

  • 정은교
    • 반도체디스플레이기술학회지
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    • 제21권1호
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    • pp.39-43
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    • 2022
  • In this paper, a study was conducted on encapsulation technology for high mechanical stability of flexible displays. First, unlike conventional encapsulation barrier that exclude cracks as much as possible for low water vapor transmission rate (WVTR), mechanical properties were improved by using a defect suppression mechanism introduced with crack arresters. The zero-stress encapsulation barrier optimizes the residual stress of the thin film based to improve the internal mechanical stability. The zero-stress encapsulation barrier was applied to the organic light emitting diodes (OLEDs) to confirm its characteristics and lifetime. Due to improved internal mechanical stability, it has a longer lifetime more than 35% compared to conventional encapsulation technologies. As the zero-stress encapsulation barrier proposed in this study does not require additional deposition process, it is not difficult to apply it. Based on various advantages, it is expected to play an important role in flexible displays.

역회복 전류억제 역률개선 회로 (Reverse Recovery Current Suppression Power Factor Correction Circuit)

  • 장덕규;신용희;김창선;박귀철
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.942-943
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    • 2008
  • The boost converter is usually used in power factor correction. The dynamic losses of its output diode are produced during the reverse recovery time. The power efficiency is decreased due to the losses and also it generates the noise. These disadvantages have been remarkably improved by ZCS and ZVS techniques of power factor improvement circuit. Some benefits lead to the achievement of higher power density and the development cost can be decreased. In this paper work, the reverse recovery suppression(RS) PFC method is used. A inductor and a diode are added into the conventional circuit. The switching device, MOSFET is turned off after the reverse recovery current has come to the zero level. The Zero Current Switching(ZCS) is implemented at that time. This power conversion technique improves the efficiency to about 1% and reduces the noise obviously. And the additional inductor can be designed using an original filter core in the circuit. The converter size is reduced effectively.

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