• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.1-6
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• 2022

In this paper, the design of lightweight S-Box structure for implementing a low power AES cryptosystem based on composite field. In this approach, the S-Box is designed as a simple structure by which the three modules of x², λ, and GF((2²)²) merge into one module for improving the usable area and processing speed on GF(((2²)²)²). The designed AES S-Box is modelled in Veilog-HDL at structural level, and a logic synthesis is also performed through the use of Xilinx ISE 14.7 tool, where Spartan 3s1500l is used as a target FPGA device. It is shown that the designed S-Box is correctly operated through simulation result, where ModelSim 10.3. is used for performing timing simulation.

• Korean Journal of Occupational Health Nursing
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• v.22 no.4
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• pp.334-342
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• 2013

Purpose: This study attempted to compare the metabolic syndrome components, liver function and heathy living habits according to abdominal obesity in male and female workers. Methods: The subjects of this study are 1,078 adult workers who visited N hospital in Incheon for health examination. The data were analyzed using t-test or $x^2$-test with the SPSS/WIN 20.0 program. Results: Prevalence of metabolic syndrome are 22.2% in male workers, and 5.2% in female workers. There were significant differences in 4 metabolic syndrome components (high blood pressure, elevated blood sugar, hypertriglyceridemia, low HDL cholesterolemia), abnormal liver function, and living habits (alcohol drinking) according to abdominal obesity in male workers. There were significant differences in 1 metabolic syndrome component (low HDL cholesterolemia), and abnormal liver function in female workers. Conclusion: It is important to manage all metabolic syndrome components and alcohol drinking in the case of male workers with abdominal obesity, and low HDL cholesterolemia in the case of female workers. Also, occupational nurses should include the relevance between abdominal obesity and liver function index when training health for workers in workplace.

• Journal of radiological science and technology
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• v.20 no.1
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• pp.91-96
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• 1997

Male rats of Albino strain were divided into four groups. The radioprotective effect of treatment with S-2(3-aminopropylamino)ethylphosphorothioic acid(WR-2721) using the dose of 200 mg/kg by intraperitonial injection on rats for 20 min prior to whole body x-ray irradiation (8 Gy) was studied. The harzardous effects of x-ray irradiation were greatly corrected In the treated group. The concentrations of total serum cholesterol, HDL-cholesterol, triglyceride, and phospholipid were greatly affected, showing insignificant changes in the treated group of animals. The drastic hyperglycemic effect of x-ray irradiation in the untreated group decreased to a normal level. These results show the potentiality of WR-2721 as a radioprotective agent.

• Journal of information and communication convergence engineering
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• v.8 no.5
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• pp.570-574
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• 2010

A thinning algorithm changes a binary fingerprint image to one pixel width. A thinning stage occupies 40% cycle of 32-bit RISC microprocessor system for a fingerprint identification algorithm. Hardware block processing is more effective than software one in speed, because a thinning algorithm is iteration of simple instructions. This paper describes an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160\times192$ Pixel Array. The ZS algorithm was applied for a thinning stage. The hardware scheme was designed and simulated in RTL. The logic was also synthesized by XST in FPGA environment. Experimental results show the performance of the proposed scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.409-416
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• 1996

This paper describes the simulation environment that verifies whether a new microporcessor described with HDL is compatible with an existing microprocessor. The compatibility verification is done by showing that the new microprocessor executes the OS(Operating System) program used in the existing microprocessor without any modification of its binary code. The proposed verification environment consists of a virtual system and a graphic user interface (GUI) module. Each module is independently designed based on serve-client model and three exists a communication part for information interchange between the two modules. This paper describes the method of constructing the verification environment and presents the compatibility verification environment of the x86 microprocessor as the simulation result.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

• Korean journal of food and cookery science
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• v.13 no.5
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• pp.639-647
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• 1997

The hypoglycemic effects of five Korean wild vegetables, Aralia continentalis (A. con.), Castanea crenata (C. cre.), Xanthium strumarium (K, str.), Alisma canaliculatum (A. can,) and Eupatorium chinense var. simplicifolium for tripartium (E. tri) which have been utilized for the traditional remedies were investigated in this study. Diabetes mellitus was induced in male Sprague-Dawley rats by injections of streptozotocin (STZ) into the tail veins at a dose of 45 mg/kg. Five groups of STZ-induced diabetic rats were fed one of each experimental diet containing 10% of the Korean wild vegetable powder and normal and STZ-control rats were fed the control diet for five weeks. The body weight change, feed efficiency ratio (FER) and organ weights were compared. The plasma levels of glucose, protein, cholesterol, HDL-cholesterol, triglyceride, free fatty acid, and aminotransferase activity were determined. Mineral (Ca, K, Mg, Na, Cu, Fe, Mn and Zn) contents of the Korean wild vegetables were analyzed. The body weight gain was higher in normal, C. cre., A. can. and E. tri. groups than in the diabetic control group. The FER of C. cre., A. can. and E. tri. groups was significantly higher (p.＜0.05) than that of diabetic control group. Liver weight was heavier in A. con., X. str. and A. can. groups compared with the diabetic control group. The weights of kidney were lighter in all five Korean wild vegetable groups than in the diabetic control group. After five weeks, the plasma glucose level tends to be decreased in A. con., A. can. and E. tri. groups. Plasma cholesterol level was decreased the Korean wild vegetables except for X. str. group. Plasma HDL- cholesterol level was significantly higher in A. con., A. can. and E. tri. groups compared with the diabetic control group. Plasma triglyceride and free fatty acid levels were significantly higher in X. str. group compared with the diabetic control group. Mineral contents were higher in E. tri. (Ca, K, Na and Fe). The results suggest that the intakes of A. con., A. can. and E. tri. have a hypoglycemic effect in diabetic rats showing the possibility as the valuable food resources for the prevention of diabetic mellitus.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.162-167
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• 2012

This paper describes the design of a high-performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.

• Journal of IKEEE
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• v.25 no.1
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• pp.10-14
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• 2021

This paper presents a hardware that improves the complexity of the CIE1931 color coordinate algorithm operation. The conventional algorithm has disadvantage of growing hardware due to 4-Split Multiply operations used to calculate large bits in the computation process. But the proposed algorithm pre-calculates the defined R2X, X2R Matrix operations of the conventional algorithm and makes them a matrix. By applying the matrix to the images and improving the color, it is possible to reduce the amount of computation and hardware size. By comparing the results of Xilinx synthesis of hardware designed with Verilog, we can check the performance for real-time processing in 4K environments with reduced hardware resources. Furthermore, this paper validates the hardware mount behavior by presenting the execution results of the FPGA board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.20-25
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• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.