• Advances in nano research
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• 제2권1호
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• pp.23-56
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• 2014

The significant growth of the Si photovoltaic industry has been so far limited due to the high cost of the Si photovoltaic system. In this regard, the most expensive factors are the intrinsic cost of silicon material and the Si solar cell fabrication processes. Conventional Si solar cells have p-n junctions inside for an efficient extraction of light-generated charge carriers. However, the p-n junction is normally formed through very expensive processes requiring very high temperature (${\sim}1000^{\circ}C$). Therefore, several systems are currently under study to form heterojunctions at low temperatures. Among them, carbon nanotube (CNT)/Si hybrid solar cells are very promising, with power conversion efficiency up to 15%. In these cells, the p-type Si layer is replaced by a semitransparent CNT film deposited at room temperature on the n-doped Si wafer, thus giving rise to an overall reduction of the total Si thickness and to the fabrication of a device with cheaper methods at low temperatures. In particular, the CNT film coating the Si wafer acts as a conductive electrode for charge carrier collection and establishes a built-in voltage for separating photocarriers. Moreover, due to the CNT film optical semitransparency, most of the incoming light is absorbed in Si; thus the efficiency of the CNT/Si device is in principle comparable to that of a conventional Si one. In this paper an overview of several factors at the basis of this device operation and of the suggested improvements to its architecture is given. In addition, still open physical/technological issues are also addressed.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1995년도 Proceedings of the Korea Automation Control Conference, 10th (KACC); Seoul, Korea; 23-25 Oct. 1995
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• pp.79-82
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• 1995

The problem of temperature control for rapid thermal processing (RTP) in semiconductor manufacturing is discussed in this paper. Among sub=micron technologies for VLSI devices, reducing the junction depth of doped region is of great importance. This paper investigates existing methods for manufacturing wafers, focusing on the RPT which is considered to be good for formation of shallow junctions and performs the wafer fabrication operation in a single chamber of annealing, oxidation, chemical vapor deposition, etc., within a few minutes. In RTP for semiconductor manufacturing, accurate and uniform control of the wafer temperature is essential. In this paper, a robustr controller is designed using a recently developed optimization technique. The controller designed is then tested via computer simulation and compared with the other results.

• 반도체디스플레이기술학회지
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• 제15권4호
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• pp.67-72
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• 2016

In this study, the texturing and the emitter formation processes were carried out with the wafer adhesion method to increase the productivity and reduce the production cost of the multi-crystalline silicon solar cell. After fabricating $156{\times}156mm$ solar cell according to the wafer adhesion method, the operation characteristics were analyzed and compared with those of the solar cell fabricated by the standard process method. In the case of a solar cell formed by the wafer adhesion method, it showed Jsc of $32.87mA/cm^2$, Voc of 0.612V, FF of 78.04% and efficiency of 15.71% respectively. The efficiency of the solar cell formed by the wafer adhesion method was 0.1% higher than that of the solar cell formed by the standard method. In addition, the productivity of the texturing and the emitter formation processes is expected to be approximately doubled. Therefore, it is expected that the manufacturing cost of the multi-crystalline solar cell can be reduced due to the improved productivity compared with the standard process.

• 전자공학회논문지D
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• 제35D권1호
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• pp.34-40
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• 1998

For applicating to 10-Gbit/s optical transimission systems, we have designed and fabricated a laser driver IC with extremely-high-operation-frequencies using AlGaAs/GaAs heterojunction bipolar transistors (HBTs), and have investigated its performances. Circuits design andsimulation were performed using SPICE and LIBRA. A discrete AlGaAs/GaAs HBT with the emitter area of 1.5*10 .mu.m$^{2}$, used for the circuit fabrication, exhibited cutoff frequency of 63 GHz andmaximum osciallation frquency of 50 GHZ. After fabrication of MMICs, we observed the very wide bandwidth of DC~18 GHz and the S$_{21}$ gain of 17 dB for a laser driver IC from the on-wafer measurement. Metal-packaged laser driver IC showed the excellent eye opening, the modulation currents of 32 mA, the rise/fall time of 40 ps, measured at the data rates of 10-Gbit/s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.677-680
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• 1999

Rapid developing automation technology enhances the need of sensors. Among many materials, silicon has the advantages of electrical and mechanical property, Single-crystalline silicon has different piezoresistivity on 야fferent directions and a current leakage at elevated temperature, but poly-crystalline silicon has the possibility of controling resistivity using dopping ions, and operation at high temperature, which is grown on insulating layers. Each wafer has slightly different thicknesses that make difficult to obtain the precisely same thickness of a diaphragm. This paper deals with the fabrication process to make poly-crystalline silicon based pressure sensors which includes diaphragm thickness and wet-etching techniques for each layer. Diaphragms of the same thickness can be fabricated consisting of deposited layers by silicon bulk etching. HF etches silicon nitride, HNO$_3$+HF does poly -crystalline silicon at room temperature very fast. Whereas ethylenediamice based etchant is used to etch silicon at 11$0^{\circ}C$ slowly.

• 한국산업보건학회지
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• 제25권1호
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• pp.36-44
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• 2015

Objectives: This study aimed to elucidate the physicochemical properties of silica powder and airborne particles as by-products generated from fabrication processes to reduce unknown risk factors in the semiconductor manufacturing work environment. Materials and Methods: Sampling was conducted at 200 mm and 300 mm semiconductor wafer fabrication facilities. Thirty-two powder and airborne by-product samples, diffusion(10), chemical vapor deposition(10), chemical mechanical polishing(5), clean(5), etch process(2), were collected from inner chamber parts from process and 1st scrubber equipment during maintenance and process operation. The chemical composition, size, shape, and crystal structure of silica by-product particles were determined by using scanning electron microscopy and transmission electron microscopy techniques equipped with energy dispersive spectroscopy, and x-ray diffractometry. Results: All powder and airborne particle samples were composed of oxygen(O) and silicon(Si), which means silica particle. The by-product particles were nearly spherical $SiO_2$ and the particle size ranged 25 nm to $50{\mu}m$, and most of the particles were usually agglomerated within a particle size range from approximately 25 nm to 500 nm. In addition, the crystal structure of the silica powder particles was found to be an amorphous silica. Conclusions: The silica by-product particles generated from the semiconductor manufacturing processes are amorphous $SiO_2$, which is considered a less toxic form. These results should provide useful information for alternative strategies to improve the work environment and workers' health.

• 대한전자공학회논문지
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• 제23권1호
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• pp.65-73
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• 1986

Experiment have been conducted about thin oxide characteristics according to O2/N2 ratio needed for EEPROM cell fabrication. As a result, we think that there is no problem even if we grow oxide layer with large O2/N2 ratio and short exidation time and when the water is implated by As before oxidation, the oxide breakdown field is about IMV/cm lower than that is not implanted. Especially, the thin oxide characteristic seems to be affected largely by wafer cleaning and oxidation in air. On the basis of these, tunnel type EEPROM cell is fabricated by 3um CMOS process and its characteristic is studied. Tunnel oxide thickness(100\ulcorner is chosen to allow Fowler-Nordheim tunneling to charge the floating gate at the desired programming voltage and tunnel area(2x2um\ulcorneris chosen to increase capacitive coupling ratio. For program operation, high voltage (20-22V) is applied to the control gate, while both drain and source are gdrounded. The drain voltage for erase is 16V. It is shown that charge retention characteristics is not limited by leakage in the oxide and program/erase endurance is over 10E4 cycles of program erase operation.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2004년도 추계학술대회 논문집
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• pp.463-467
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• 2004

This paper presents the fabrication possibility of the micro actuator which uses a micro-thermal bubble, generated b micro-heater under pulse heating. The valve-less micropump using the diffuser/nozzle is consists of the lower plate, he middle plate, the upper plate. The lower plate includes the channel and chamber are fabricated on high processability silicon wafer by the DRIE(Deep Reactive Ion Etching) process. The middle plate includes the chamber and diaphragm d the upper plate is the micro-heater. The Micropump is fabricated by bonding process of the three layer. This paper resented the possibility of the PCR chip operation by the fabricated micropump.

• Journal of the Optical Society of Korea
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• 제9권1호
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• pp.16-21
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• 2005

Using a cantilever type nanoprobe having a 100㎚m aperture at the apex of the pyramidal tip of a near-field scanning optical microscope (NSOM), nanopatterning of polymer films are conducted. Two different types of polymer, namely a positive photoresist (DPR-i5500) and an azopolymer (Poly disperse orange-3), spincoated on a silicon wafer are used as the substrate. A He-Cd laser with a wavelength of 442㎚ is employed as the illumination source. The optical near-field produced at the tip of the nanoprobe induces a photochemical reaction on the irradiated region, leading to the fabrication of nanostructures below the diffraction limit of the laser light. By controlling the process parameters properly, nanopatterns as small as 100㎚ are produced on both the photoresist and azopolymer samples. The shape and size variations of the nanopatterns are examined with respect to the key process parameters such as laser beam power, irradiation time or scanning speed of the probe, operation modes of the NSOM (DC and AC modes), etc. The characteristic features during the fabrication of ordered structures such as dot or line arrays using NSOM lithography are investigated. Not only the direct writing of nano array structures on the polymer films but also the fabrication of NSOM-written patterns on the silicon substrate were investigated by introducing a passivation layer over the silicon surface. Possible application of thereby developed NSOM lithography technology to the fabrication of data storage is discussed.

• 한국산업보건학회지
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• 제26권1호
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• pp.58-63
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• 2016

Objectives: One major limitation encountered in retrospective exposure assessment for epidemiological study is the lack of exposure records and information maintained by companies which if they existed would allow the estimation of past exposure to hazardous operations and agents. This study developed a job-specific questionnaire(JSQ) to estimate exposure profiles among semiconductor workers, including operation and job. Methods: This JSQ can be directly applied to workers who work or have worked in a wafer fabrication or a chip packaging and assembly facility. Results and Conclusions: We used this JSQ to obtain past exposure information from semiconductor workers via face-to-face investigation. Major contents include questions on the facilities, operations and jobs to which they have been exposed since they entered employment in the semiconductor industry. The total number of questions in the JSQ is 18. Responses to this JSQ can be used not only to estimate retrospective exposure to operations and jobs in the semiconductor industry, but also to associate with the risk of all causes of death and risk of disease, including cancer.