• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.160-163
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• 2002

Micro via hole Fabrication is studied by means of minimizing method to circuit size as many electric products developed to portable and minimize. Most of currently micro via hole fabrication using laser is that fabricate insulator layer using CO2 Laser after Cu layer by etching, or fabricate insulator layer using IR after trepanning Cu by UV. In this paper, it was performed that a metal layer and insulator layer were worked upon only one UV laser, and increase to processing speed by experiment.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.627-629
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• 2000

최근에 클러스터 시스템 사용이 보편화되어 가고 있지만 클러스터를 구성하고 있는 노드 사이의 통신이 여전히 전체 성능 향상의 병목요인으로 지적되어 있다. 현재 클러스터 시스템의 노드간 통신은 TCP 프로토콜을 이용하고 있는데, 동질적이고 전송에러를 무시할 수 있는 클러스터 통신망에는 적합하지 않다. TCP의 단점을 극복하기 위하여 클러스터를 위한 다양한 사용자 수준 인터페이스가 제안되고 구현되었다. 이 중 Intel, Compaq, Microsoft가 주축이 되어 정의한 VIA는 SAN 환경에 적합하도록 기존의 소프트웨어 오버헤드를 줄인 사용자 수준의 통신 프로토콜이다. 본 논문에서는 현재 리눅스 클러스터 상에서 사용 가능한 VIA 구현들에 대해 특징을 살펴보고, 동일한 환경에서 성능을 비교해 보았다.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.557-565
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• 2005

This paper presents the development and implementation of a zero-copy file transfer mechanism that improves the efficiency of file transfers for PC cluster systems using hardware-based VIA(Virtual Interface Architecture) network adapters. VIA is one of the representative user-level communication interfaces, but because there is no library for file transfer, one copy occurs between kernel buffer and user boilers. Our mechanism presents a file transfer primitive that does not require the file system to be modified and allows the NIC to transfer data from the kernel buffer to the remote node directly without copying. To do this, we have developed a hardware-based VIA network adapter, which supports the PCI 64bit/66MHz bus and Gigabit Ethernet, as a NIC, and implemented a zero-copy file transfer mechanism. The experimental results show that the overhead of data coy and context switching in the sender is greatly reduced and the CPU utilization of the sender is reduced to $30\%\~40\%$ of the VIA send/receive mechanism. We demonstrate the performance of the zero-copy file transfer mechanism experimentally. and compare the results with those from existing file transfer mechanisms.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.99-104
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• 2015

The requirement for success of via filling is its ability to fill via holes completely without producing voids or seams. Defect free via filling was obtained by optimizing plating conditions such as current mode, current density and additives. However, byproducts stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this study, the relationship between JGB and current density on the copper via filling was investigated without the addition of other additives to minimize the contamination of copper via. AR 4 with $15{\mu}m$ diameter via were used for this study. The pulse current was used for the electroplating of copper and the current densities were varied from 10 to $20mA/cm^2$ and the concentrations of JGB were varied from 0 to 25 ppm. The map for the JGB concentration and current density was developed. And the optimum conditions for the AR 4 via filling with $15{\mu}m$ diameter were obtained.

• Korean Membrane Journal
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• v.8 no.1
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• pp.1-12
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• 2006

In semiconductor industries, dissolved oxygen is one of the most undesirable contaminants of ultrapure water. A method for dissolved oxygen removal (DOR) consists in the use of polymeric hollow fibres, loaded with a catalyst and fed with a reducing agent such as hydrogen. In this work, PVDF hollow fibres loaded with Pd were characterized by means of perporometry, scanning electron microscopy (SEM), energy dispersive X-ray (EDX). The hollow fibre analyzed shows a five-layer structure with remarkable morphological differences. An estimation of pore diameters and their distribution was performed giving a mean pore diameter of 100 nm. The permeance and selectivity of the fibres were measured using $H_2,\;N_2,\;O_2$ as single gases, at different operating conditions. An $H_2$ permeance of $37 mmol/m^2s$ was measured and $H_2/O_2$ and $H_2/N_2$ selectivities of ca. 3 were obtained. $H_2$ permeance was 1/3 when a water stream flows in the shell side. Catalytic fibrebehaviour was simulated using a mathematical model for a loop membrane reactor, considering only $O_2$ and $H_2$ diffusive transport inside the membrane and their catalytic reaction. Dimensionless parameters such as the Thiele modulus are employed to describe the system behaviour. The model agrees well with the experimental reaction data.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.209-209
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• 2007

Passive Device는 RF Circuit을 제작할 때 많은 면적을 차지하고 있으며 이를 감소시키기 위해 여러 연구가 진행되고 있다. 최근 SoP-L 공정을 이용한 많은 연구가 진행되고 있는데 PCB 제작에 이용되는 일반적인 재료와 공정을 그대로 이용함으로써 개발 비용과 시간 면에서 많은 장점을 가지기 때문이다. SoP-L의 또 하나 장점은 다층구조를 만들기가 용이하다는 점이다. 각 층 간에는 Via를 사용하여 연결하게 되는데, RF Circuit은 회로의 구조와 물성에 따라 특성이 결정되며, 그만큼 Via를 썼을 때 그 영향을 생각해야 한다. 본 연구에서는 multi-layer LCP substrate에 다수의 Via를 chain 구조로 형성하여 전기적 특성을 확인하였다. Via가 70um 두께의 substrate를 관통하면서 상층과 하층의 Conductor을 연속적으로 연결하게 된다. 이 구조의 Resistance와 Insertion Loss를 측정하여, Via의 크기 별 수율과 평균적인 Resistance, RF 계측기로 재현성을 확인하였다. 이를 바탕으로 공정에서의 안정성을 확보하고 Via의 크기와 도금방법에 의한 RF Circuit에서의 영향을 파악하여, 앞으로의 RF Device 개발에 도움이 될 것으로 기대한다. 특히 유기물을 이용한 다층구조의 고주파 RF Circuit에 Via를 적용할 때의 영향을 설계에서부터 고려할 수 있는 자료가 될 것이다.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.4
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• pp.192-200
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• 2002

The performance of a PC cluster system is limited by the use of traditional communication protocols, such as TCP/IP because these protocols are accompanied with significant software overheads. To overcome the problem, systems based on user-level interface for message passing without intervention of kernel have been developed. The VIA(Virtual Interface Architecture) is one of the representative user-level interfaces which provide low latency and high bandwidth. In this paper, a VIA system is implemented on an SCI(Scalable Coherent Interface) network based PC cluster. The system provides both message-passing and shared-memory programming environments and shows the maximum bandwidth of 84MB/s and the latency of $8{\mu}s$. The system also shows better performance in comparison with other comparable computer systems in carrying out parallel benchmark programs.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.39-43
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• 2012

Via-filling plating and through-hole plating are absolutely imperative for manufacturing of printed-wiring board. This Paper is introducing the latest developments of our company worked on the high-performance of acid copper plating additives for them.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.699-700
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• 2009