• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.20-20
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• 2004

• Honam Mathematical Journal
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• v.26 no.3
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• pp.281-286
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• 2004

We calculate the harmonic series $E_{2p}:=^P\;_{^{\infty}_{n=1}}{\frac{1}{n^{2p}}$ via Waring's formula.

• Bulletin of the Korean Chemical Society
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• v.23 no.8
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• pp.1157-1159
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• 2002

• Bulletin of the Korean Chemical Society
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• v.12 no.2
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• pp.157-163
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• 1991

The total synthesis of dihydroreynosin (1) and dihydrosantamarine (2) via tandem Cope-Claisen rearrangement has been accomplished starting from (S)-carvone (4).

• Computers and Concrete
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• v.15 no.6
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• pp.951-972
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• 2015

The focus of the present study is to investigate both local and global behaviour of a precast concrete sandwich panel. The selected prototype consists of two reinforced concrete layers coupled by a system of cold-drawn steel profiles and one intermediate layer of insulating material. High-definition nonlinear finite element (FE) models, based on 3D brick and 2D interface elements, are used to assess the capacity of this technology under shear, tension and compression. Geometrical nonlinearities are accounted via large displacement-large strain formulation, whilst material nonlinearities are included, in the series of simulations, by means of Von Mises yielding criterion for steel elements and a classical total strain crack model for concrete; a bond-slip constitutive law is additionally adopted to reproduce steel profile-concrete layer interaction. First, constitutive models are calibrated on the basis of preliminary pull and pull-out tests for steel and concrete, respectively. Geometrically and materially nonlinear FE simulations are performed, in compliance with experimental tests, to validate the proposed modeling approach and characterize shear, compressive and tensile response of this system, in terms of global capacity curves and local stress/strain distributions. Based on these experimental and numerical data, the structural performance is then quantified under various loading conditions, aimed to reproduce the behaviour of this solution during production, transport, construction and service conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.55-67
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• 2010

The electrical properties of a back drilled via-hole (BDH) without the open-stub and the plated through via-hole (PTH) with the open-stub, which is called the conventional structure, in a high-count multi~layered (HCML) printed circuit board (PCB) were investigated for a high-speed digital system, and a selected inner layer to transmit a high-speed signal was farthest away from the side to mount the component. Within 10 GHz of the broadband frequency, a design of experiment (DOE) methodology was carried out with three cause factors of each via-hole structure, which were the distance between the via-holes, the dimensions of drilling pad and the anti-pad in the ground plane, and then the relation between cause and result factors which were the maximum return loss, the half-power frequency, and the minimum insertion loss was analyzed. Subsequently, the empirical formulae resulting in a macro model were extracted and compared with the experiment results. Even, out of the cause range, the calculated results obtained from the macro model can be also matched with the measured results within 5 % of the error.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.51-56
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• 2012

In order to fabricate through-Si-vias for thermal vias by using wet etching process, anisotropic etching behavior of Si substrate was investigated as functions of concentration and temperature of TMAH solution in this study. The etching rate of 5 wt%, 10 wt%, and 25 wt% TMAH solutions, of which temperature was maintained at $80^{\circ}C$, was $0.76{\mu}m/min$, $0.75{\mu}m/min$, and $0.30{\mu}m/min$, respectively. With changing the temperature of 10 wt% TMAH solution to $20^{\circ}C$ and $50^{\circ}C$, the etching rate was reduced to $0.067{\mu}m/min$ and $0.233{\mu}m/min$, respectively. Through-Si-vias of $500{\mu}m$-depth could be fabricated by etching a Si substrate for 5 hours in 10 wt% TMAH solution at $80^{\circ}C$ after forming same via-pattern on each side of the Si substrate.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.117-123
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• 2014

Cu through-vias, which can be used as thermal vias or vertical interconnects, were formed using bottom-up electrodeposition filling as well as top-down electrodeposition filling into open via-holes and their microstructures were observed. Solid Cu through-vias without voids could be successfully formed by bottom-up filling as well as top-down filling with direct-current electrodeposition. While chemical-mechanical polishing (CMP) to remove the overplated Cu layer was needed on both top and bottom surfaces of the specimen processed by top-down filling method, the bottomup process has an advantage that such CMP was necessary only on the top surface of the sample.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.75-75
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• 2010

3D 패키징 기술은 전기소자의 소형화, 고용량화, 저전력화, 높은 신뢰성등의 요구와 함께 그 중요성이 대두대고 있다. 이러한 3D 패키징의 연결방법은 와이어 본딩 또는 플립칩등의 기존의 방법에서 TSV(Through Silicon Via)를 이용하여 적층하는 방법이 주목받고 있다. TSV는 기존의 와이어 본딩과 비교하여 고집적도, 빠른 신호전달, 낮은 전력소비 등의 장점을 가지고 있어 많은 연구가 진행되고 있다. TSV의 세부 공정 중 비아필링(Via filling)기술은 I/O수 증가와 미세피치화에 따른 비아(Via) 직경의 감소 및 종횡비(Via Aspect Ratio)증가로 인해 기존 필링 공정으로는 한계가 있다. 기존의 비아 홀(Via hole)에 금속을 필링하기 위한 방법으로 전기도금법이 많이 사용되고 있으나, 전기도금법은 전기도금액 조성, 첨가제의 종류, 전류밀도, 전류모드 등에 따라 결과물에 큰 차이가 발생되어, 최적공정조건의 도출이 어렵다. 또한 20um이하의 비아직경과 높은 종횡비로 인하여 충진시 void형성등의 문제점이 발생하기도 한다. 본 연구에서는 용융솔더와 진공을 이용하여 비아를 필링시켰다. 이 방법은 관통된 비아가 형성된 웨이퍼 양단에 압력차를 주어, 작은 직경을 갖는 비아 홀의 표면장력을 극복하고, 용융상태의 솔더가 관통된 비아 홀 내부로 필링되는 방법이다. 관통 비아홀이 형성 된 웨이퍼 위에 솔더페이스트를 $250^{\circ}C$이상 온도를 가해 용융상태로 만든 후 웨이퍼 하부에 진공을 형성하여 필링하는 방법과 용융솔더를 노즐을 통하여 위쪽으로 유동시켜 그 위에 비아홀이 형성된 웨이퍼를 접촉하고 웨이퍼 상부에 진공을 형성하여 필링하는 방법으로 실험을 각각 실시하였다. 이 때, 웨이퍼 두께는 100um이하이며 홀 직경은 20, 30um, 웨이퍼 상부와 하부의 진공차는 약 0.02~0.08Mpa, 진공 유지시간은 1~3s로 실시하여 최적 조건을 고찰하였다. 각 조건에 따른 필링 후 단면을 전자현미경(FE-SEM)을 통해 관찰하였다. 실험 결과 0.04Mpa 이상에서 1s내의 시간에 모든 비아홀이 기공(Void)없이 완벽하게 필링되는 것을 관찰하였으며 이 결과는 기존의 방법에 비하여 공정시간을 감소시켜 생산성이 대폭 향상 될 수 있는 방법임을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.56-66
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• 2012

The inductive loaded patch antenna with suppressed radiation along the horizontal plane and enhanced broadside gain is investigated by adjusting the width and the via radius of a unit cell at a fixed length of a unit cell. The effects of the via radius and the width of the unit cell on the dispersion characteristics of the inductive loaded transmission line are investigated. The systematic study to determine the via radius and the width of the unit cell for the effective dielectric constant of the inductive loaded patch antenna close to 1 in order to suppress the radiation along the horizontal plane is presented. Inductive loaded patch antennas composed of five unit cells with resonant frequency of 5 GHz are designed and their radiation characteristics are presented. The horizontal radiation along the E-plane is greatly suppressed to less than -15 dBi when the effective dielectric constant of the inductive loaded patch antenna is slightly less than 1.