• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.15-16
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• 2012

This paper is study on a novel high efficiency step up-down converter using loss-less snubber capacitor. The proposed converter is accomplished that the turn-on operation of switches is on zero current switching (ZCS) by DCM. The converter is also applicable to a new quasi-resonant circuit to achieve high efficiency converter. The control switches using in the converter are operated with soft switching, that is, ZVS and ZCS by quasi-resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the converter is high.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.263-266
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• 2003

The high power factor converters are classified step-up, step-up-down and step-down converter, The power conversion system must be increased switching frequency in order to achieve a small size, a light weight and a low noise. And the power system brings on a high efficiency and high power factor. When a switch of the step down converter is operated with a commercial frequency(60Hz), a reactor using the converter is gone with a great number of harmonics waveforms of low grade. As results of this, the converter is decreased input power factor and is increased system size. To improved these, this paper proposes a PSM(Pulse Size Modulation) control strategy operated with high power factor.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1629-1638
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• 2016

Differential power processing (DPP) systems are among the most effective architectures for photovoltaic (PV) power systems because they are highly efficient as a result of their distributed local maximum power point tracking ability, which allows the fractional processing of the total generated power. However, DPP systems require a high-efficiency, high step-up/down bidirectional converter with broad operating ranges and galvanic isolation. This study proposes a single, magnetic, high-efficiency, high step-up/down bidirectional DC-DC converter. The proposed converter is composed of a bidirectional flyback and a bidirectional isolated switched-capacitor cell, which are competitively cheap. The output terminals of the flyback converter and switched-capacitor cell are connected in series to obtain the voltage step-up. In the reverse power flow, the converter reciprocally operates with high efficiency across a broad operating range because it uses hard switching instead of soft switching. The proposed topology achieves a genuine on-off interleaved energy transfer at the transformer core and windings, thus providing an excellent utilization ratio. The dynamic characteristics of the converter are analyzed for the controller design. Finally, a 240 W hardware prototype is constructed to demonstrate the operation of the bidirectional converter under a current feedback control loop. To improve the efficiency of a PV system, the maximum power point tracking method is applied to the proposed converter.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.3
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• pp.433-437
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• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.961-965
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• 2006

Design Up/Down converters which use Digital IF( Intermediate Frequency) techniques from the present paper, against hereupon performance the criticism. The reason which uses Digital IF techniques is configured of passive elements and the position If frequency domains are fixed and they do not use in the position one frequency but, the external fringe land of the board which comes to be configured with Digital IF without from the communication frequency domain which is various there to be a flexibility, the use was under possibility. Like this configuration compares in analog Heterodyne mode of existing and it has the performance upgrade which is excellent it shows a high flexibility.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.69.6-69
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• 2001

The SSPA makes the power level of EIRP up to 16W, and compensates for temperature to the SSPA´s maximum stability. The up and the down converters are dually conversed like as individual synthesizers for selecting of independent transmit-receive transponder. The function of the up-converter is to convert the 70MHz IF signal modulated in the indoor unit modem into a 14.0 ∼ 14.5 GHz Ku-band up-link signal to be sent to the antenna. The down-converter converts the 12.25 ∼ 12.75 GHz Ku-band down-link signal or a trouble malfunction of SSPA may be a fatal factor to operation of the whole satellite communication network. Therefore, this study developed the remote monitoring and control program to monitor the SSPA´s status before the problem occurs for stable operation of the system. This software ...

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.34-36
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• 2008

This paper is given a full detail of mathematical analyses of input current for novel active type power factor correction(PFC) AC-DC converter of step up-down added electric isolation. These are compared with harmonics components of input current for a conventional PFC converter of electric isolation type. The proposed PFC converter is constructed in using a new loss-less snubber circuit to achieve a soft switching of control device. Also the proposed converter for discontinuous conduction mode(DCM) eliminates the complicated circuit control requirement and reduces the size of components. The input current waveform in the proposed converter is got to be a sinusoidal form of discontinuous pulse in proportion to magnitude of ac input voltage under the constant duty cycle switching. Therefore, input power factor is nearly unity and the control method is simple. Particularly, the stored energy of loss-less snubber capacitor is recovered with input side and increases input current from resonant operation. The result is that input power factor of the proposed converter is higher than that of a conventional PFC converter. Some simulative results on computer and experimental results are included to confirm the validity of the analytical results.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.467-472
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• 2005

In this paper, design and control of the novel SEPIC-Flyback converter(SF converter) is developed as a possible converter for fuel cell system. This output characteristic of SF converter is similar to Buck-Boost converter in that it can step-up or step-down the voltage. With the small signal equivalent circuit modeling of SF converter, control-to-output transfer function is obtained. SF converter couples up the inductive type converter to capacitive type converter with one transformer, which has less ripple current than its respective one does. To verify the validity of the proposed converter, 500W, 100kHz converter is designed and tested. ZVS switching and active clamping are also tested in practice.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.891-894
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• 2003

본 논문에서는 3-상 클럭을 이용하여 UP/DOWN 변환을 동시에 수행하는 DC/DC 변환기의 설계에 대해 설명한다. 기존의 UP/DOWN DC/DC 변환기의 경우에는 한 스텝당 변화하는 전압의 양이 많아서 출력에 수십 mV의 리플이 존재하게 된다. 이 리플을 줄이기 위해서는 L, C의 값을 크게 해 주어야하는 문제가 있다. 그러나, 설계된 UP/DOWN DC/DC 변환기는 기존의 UP/DOWN DC/DC 변환기의 구조를 가지면서, 3-상 클럭을 이용하여 한 스텝당 변화하는 전압의 양을 작게 하여 작은 L, C의 값을 가지고도 4mV이하의 출력 리플을 갖는 안정된 전압 변환을 하도록 설계하였다. 설계된 변환기는 0.25㎛ standard CMOS 공정을 이용하여 구현하였다. 구현 된 칩의 면적은 1.8 mm × 0.8 mm이다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1023-1026
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• 2005

본 논문에서는 SDR(Software Defined Radio) 시스템을 위한 Digital IF(Intermediate Frequency) Up/Down 변환기를 설계하고 성능을 평가하였다. 설계한 시스템은 AD 변환부, DA 변환부 및 Up-Down conversion 기능을 수행하는 FPGA로 구성된다. AD 변환부는 Analog Device 사의 AD6645를 사용하였으며, DA 변환부는 Analog Device 사의 AD9775를 사용하였다. Up-Down conversion 기능을 수행하는 FPGA부는 샘플된 IF 입력을 혼합기와 NCO에 의해 기저대역(DC)으로 다운 시키는 역할을 하며, 14bit의 기저대역(DC) 신호를 혼합기와 NCO에 의해 IF 출력으로 올려주는 역할을 한다. 이러한 설계는 기존의 아날로그 헤테로다인 방식에 비하여 높은 유연성 및 우수한 성능 향상을 보여준다.