• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.684_685
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• 2009

A digital sampling algorithm that uses a two high resolution integrating Voltmeters which are synchronized by Phase Lock Loop (PLL) time clock for accurately measuring the parameters, active and reactive power, for sinusoidal power measurements is presented. The PLL technique provides high precision measurements, root mean square (rms), phase and complex voltage ratio, of the AC signal. The system has been designed to be used at the Korean Research Institute of Standards and Science (KRISS) as a reference power standard for electrical power calibrations. The test results have shown that the accuracy of the measurements is better than $10 {\mu}W/VA$ and the level of uncertainty is valid for the power factor range zero to 1 for both lead and lag conditions. The system is fully automated and allows power measurements and calibration of high precision wattmeters and power calibrators at the main power frequencies 50 and 60 Hz.

• 한국지능시스템학회논문지
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• 제10권5호
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• pp.478-486
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• 2000

본 논문에서는 CMOS 디지털 회로상의 플립플롭의 위치를 이동시키는 리타이밍 변환에 유전자 알고리즘을 적용하여 회로의 최적 동작 속도를 유지하면서 전력의 소모를 줄일 수 있는 설계 방법을 제안한다. 제안된 설계 방법은 최적 속도를 구현하는 리타이밍 단계와 유전자 알고리즘이 적용되는 저전력 리타이밍의 두 단계로 이루어진다. 제안된 저전력 리타이밍 설계 도구를 예제 회로의 설계에 적용하고 설계된 회로의 성능을 Synopsys시의 Design Analyzer로 평가한 결과, 임계 경로 지연은 약 30~50% 가량 감소하였으며 동적 전력 소모는 약 1.4~18.4% 가량 감소함을 관찰하였다.

• 대한전자공학회논문지SD
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• 제44권2호
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• pp.19-24
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• 2007

최근 대용량 데이터 전송이 이루어지면서 하드웨어의 복잡성과 전력, 가격 등의 이유로 인하여 입력데이터와 클럭을 함께 수신 단으로 전송하는 병렬버스 기법보다는 시리얼 링크 기법이 메모리 인터페이스에 많이 사용되고 있다. 시리얼 링크 기법은 병렬버스 기법과는 달리 클럭을 제외한 데이터 정보만을 수신단으로 보내는 방식이다. 클럭 및 데이터 복원 회로(clock and data recovery 혹은 CDR)는 시리얼 링크의 핵심 블록으로, 본 논문에서는 그래픽 DRAM 인터페이스용의 5.4Gb/s half-rate bang-bang 클럭 및 데이터 복원회로를 설계하였다. 이 회로는 half-rate bang-bang 위상검출기, current-mirror 전하펌프, 이차 루프필터, 및 4단의 차동 링타입 VCO로 구성되었다. 위상 검출기의 내부에서 반 주기로 DeMUX된 데이터를 복원할 수 있게 하였고, 전체 회로의 용이한 검증을 위해 MUX를 연결하여, 수신된 데이터가 제대로 복원이 되는지를 확인하였다. 설계한 회로는 66㎚ CMOS 공정파라미터를 기반으로 설계 및 layout하였고, post-layout 시뮬레이션을 위해 5.4Gb/s의 $2^{13}-1$ PRBS 입력데이터를 사용하였다. 실제 PCB 환경의 유사 기생성분을 포함하여 시뮬레이션 한 결과, 10psRMS 클럭 지터 및 $40ps_{p-p}$ 복원된 데이터 지터 특성을 가지고, 1.8V 단일 전원전압으로부터 약 80mW 전력소모를 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• 한국운동역학회지
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• 제24권4호
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• pp.417-423
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• 2014

The purpose of this study was to compare two saddle height determination methods by the effectiveness of pedal reaction force. Ten male subjects (age: $24.0{\pm}2.4years$, height: $175.1{\pm}5.4cm$, weight: $69.3{\pm}11.1kg$, inseam: $77.8{\pm}4.5cm$) participated in three minutes, 60 rpm cycle pedaling tests with the same load and cadence. Subject's saddle height was determined by $25^{\circ}$ knee flexion angle (K25) when the pedal crank was at the 6 o'clock position (knee angle method) and 97% (T97), 100% (T100), 103% (T103) of trochanter height (trochanteric method). The RF (resultant force), EF (effective force), and IE (index of effectiveness) were compared by measuring 3D motion and 3-axis pedal reaction force data during 4 pedaling phases (phase1: $330^{\circ}-30^{\circ}$, phase2: $30^{\circ}-150^{\circ}$, phase3: $150^{\circ}-210$, phase4: $210^{\circ}-330^{\circ}$). Results showed that there were significant differences in EF at phase1 between T97 and K25, in EF at phase4 between T100 and T103, in IE at total phase between T97 and K25, between T100 and T103, in IE at phase1 & phase2 between T97 and K25. There was higher IE in the K25 than any other saddle heights, which means that K25 was better pedaling effectiveness than the trochanteric method. Therefore it was suggested the saddle height as 103.7% of trochanter height that converted from K25.

• Journal of Positioning, Navigation, and Timing
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• 제4권1호
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• pp.25-31
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• 2015

In this paper, we described the timing-offset comparison results between various daily jump compensation methods for GPS carrier phase (CP) measurement data. For the performance comparison, we used about 70 days GPS measurement data obtained from two GPS geodetic receivers which share the reference 1 PPS and RF signals and closely located in each other within a few meters. From the experiment results, the followings were observed. First, daily jumps existed in CP measurements depend on not only the environment but also the receiver which will make a full compensation be very hard or impossible. Second, clock bias can be occurred in the case of using a simple compensation with accumulation of daily jumps but it could be used in a short-period frequency comparison campaign (less than about 7 days) despite of its drawback.

• 대한전자공학회논문지TC
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• 제38권12호
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• pp.1-9
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• 2001

APON(ATM Passive Optical Network)에서, 상향 트래픽의 전송은 OLT가 ONU에게 타임슬롯을 할당하여 셀을 보내게 하는 TDMA(Time Division Multiple Access) 방식을 근간으로 한다. 상향은 스트림 모드가 아니기 때문에, 셀 동기 장치는 버스트 모드로 동작해야 한다. 또한, 하나의 광섬유에 여러 대의 ONU가 보내는 셀들 사이에서 충돌을 방지하기 위하여 셀 위상 감시기가 필요하다. 본 논문에서는 G.983.1 기반의 APON에서 상향 셀 전송을 위해 사용될 수 있는 TDMA 버스트 셀 동기장치를 FPGA(Field Programmable Gate Array)로 구현한다. 이 동기장치는 상향 데이터 복구(data recovery) 기능과 위상 감시 (Phase Monitoring)라는 두가지 주된 기능이 있다. 전자는 상향 타임슬롯의 오버헤드에서 preamble을 찾고 비트 및 셀 위상을 시스템 클럭에 정렬함으로써, OLT에서 상향 데이터와 클럭을 복구하기 위한 것이다. 후자는 상향 셀 충돌을 방지하기 위하여 인접 셀 간의 위상편차를 지속적으로 감시함으로써, 각 ONU에게 등화지연(equalization delay)을 보정할 수 있도록 정보를 제공하기 위한 것이다.

• 한국운동역학회지
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• 제26권3호
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• pp.303-308
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• 2016

Objective: This study evaluated the vertical and horizontal forces in the frontal plane acting on a pedal due to the vertical alignment of the lower limbs. Method: Seven male subjects (age: $25.3{\pm} 0.8years$, height: $175.4{\pm}4.7cm$, weight: $74.7{\pm}14.2kg$, foot size: $262.9{\pm}7.6mm$) participated in two 2-minute cycle pedaling tests, with the same load and cadence (60 revolutions per minute) across all subjects. The subject's saddle height was determined by the height when the knee was at $25^{\circ}$ flexion when the pedal crank was at the 6 o'clock position (knee angle method). The horizontal force acting on the pedal, vertical force acting on the pedal in the frontal plane, ratio of the two forces, and knee range of motion in the frontal plane were calculated for four pedaling phases (phase 1: $330{\sim}30^{\circ}$, phase 2: $30{\sim}150^{\circ}$, phase 3: $150{\sim}210^{\circ}$, phase 4: $210{\sim}330^{\circ}$) and the complete pedaling cycle. Results: The range of motion of the knee in the frontal plane was decreased, and the ratio of vertical force to horizontal force and overall pedal force in the complete cycle were increased after vertical alignment. Conclusion: The ratio of vertical force to horizontal force in the frontal plane may be used as an injury prevention index of the lower limb.

• 센서학회지
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• 제21권5호
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• pp.389-393
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• 2012

A chaotic oscillator with light controllability was designed. The proposed chaotic oscillator consists of a photo sensor, two phase clock driven MOS switches, nonlinear function blocks for chaotic signal generation. SPICE circuit analysis using a 0.35 um CMOS process parameters was performed for its chaotic dynamics. And we confirmed that chaotic behaviors of the circuit can be controlled according to light intensity. By SPICE simulation, chaotic dynamics by time waveforms, frequency analysis was analyzed. SPICE results showed that proposed circuit can make various light-controlled chaotic signals.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.149-152
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• 1998

A synchronization is very important element not only wire communication but also wireless communication. A synchronous oscillator(SO) is a network which synchronizes, tracks, filter, amplifies and divides (if necessary) in a single process. The coherent phase synchronous oscillator(CPSO) is created by adding two external loops to the SO. The CPSO ratains all virtues of a SO while providing coherency throughout the tracking range. This paper has applied a clock recovery of GPS signal using CPSO.