• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.10-17
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• 2012

This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.425-435
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• 2016

This paper describes a spread-spectrum clock generation method by utilizing a ${\Delta}{\Sigma}$ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order ${\Delta}{\Sigma}$ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The ${\Delta}{\Sigma}$ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.593-596
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• 2002

A design of clock and data recovery (CDR) circuit for the SONET OC-48 using a standard 0.18 ${\mu}m$ CMOS process has been performed. The phase detector and the charge pump must be able to operate at the 2.5 Gb/s input data speed and also accurately compare phase errors to reduce clock jitter. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output. A general ring oscillator topology is presented and simulated. It provides five-phase outputs and 220 MHz to 3.12 GHz tuning range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.80-86
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• 2009

In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations and measurements demonstrates that the proposed charge pump exhibits the higher output voltage, the larger output current and a better power efficiency over the traditional twin-well charge pumps.

• Proceedings of the KSRS Conference
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• 2008.10a
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• pp.277-280
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• 2008

Enhancing the positioning precision is the primary pursuit of GPS users. To achieve this goal, most studies have focused on the relationship between GPS receiver clock errors and GPS positioning precision. This study utilizes undifferentiated phase data to calculate GPS clock errors and to compare with the frequency of cesium clock directly, thus verifying estimated clock errors by the method used in this paper. The relative frequency offsets from this paper and from National Standard Time and Frequency Laboratory of Taiwan match to $1.5{\times}10^{12}$ in the frequency instability, suggesting that the proposed technique has reached a certain level of quality. The built-in quartz clocks in the GPS receivers yield relative frequency offsets that are 3 to 4 orders higher than those of rubidium clocks. The frequency instability of the quartz clocks is on average two orders worse than that of the rubidium clock. Using the rubidium clock instead of the quartz clock, the horizontal and vertical positioning accuracies were improved by 26-78% (0.6-3.6 mm) and 20-34% (1.3-3.0 mm), respectively, for a short baseline. These improvements are 7-25% (0.3-1.7 mm) and 11% (1.7 mm) for a long baseline. Our experiments show that the frequency instability of clock, rather than relative frequency offset, is the governing factor of positioning accuracy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.3
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• pp.68-76
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• 1985

A charge-coupled device (CCD) area image sensor has been demonstrated with an experi-mental 16$\times$16 prototype. The prototype is a vertical frame transfer charge.coupled imager using two-phase gate electrode structures. In this device, ion-implanted barriers are used for two -phase CCD, and NMOS process has been adopted. The total imaging setup consisting of optical lens, clock generators, clock drivels, staircase signal generators, and oscilloscope is easily achieved with the aid of PROM . English alphabets are displayed on the oscilloscope screen using the total imaging set-up. We measure charge transfer inefficiency and dark current for the fabricated devices.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.309-314
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• 2006

In general DGPS system, the correction message is transferred to users by wireless modem. To cover wide area, many DGPS station should be needed. And DGPS users must have a wireless modem that is not necessary in standalone GPS. But SBAS users don't need a wireless modem to receive DGPS corrections because SBAS correction message is transmitted from the GEO satellite by L1 frequency band. SBAS signal is generated in the GUS(Geo Uplink Subsystem) and uplink to the GEO satellite. This uplink transmission process causes two problems that are not existed in GPS. The one is a time delay in the uplink signal. The other is an ionospheric problem on uplink signal, code delay and carrier phase advance. These two problems cause ranging error to user. Another critical ranging error factor is clock synchronization. SBAS reference clock must be synchronized with GPS clock for an accurate ranging service. The time delay can be removed by close loop control. We propose uplink ionospheric error correcting algorithm for C/A code and carrier. As a result, the ranging accuracy increased high. To synchronize SBAS reference clock with GPS clock, I reviewed synchronization algorithm. And I modified it because the algorithm didn't consider doppler that caused by satellites' dynamics. SBAS reference clock synchronized with GPS clock in high accuracy by modified algorithm. We think that this paper will contribute to basic research for constructing satellite based DGPS system.