• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.241-249
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• 2003

Carry lookahead(CLA) circuitry of decimal adders is proposed aiming at delay reduction. The truncation error in calculation of monetary interests may accumulate yielding a substantial amount of errors. Binary Coded Decimal(BCD) additions. for example, eliminate the truncation error in a fractional representation of decimal numbers. The proposed BCD carry lookahead scheme is aiming at the speed improvements without any truncation errors in the addition of decimal fractions. The delay estimation of the BCD CLA is demonstrated with improved performance in addition. Further reduction in delay can be achieved introducing non-weighted number system such as the excess-3 code.

• Journal of the Korean Mathematical Society
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• v.47 no.6
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• pp.1299-1316
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• 2010

We derive estimates for the truncation, amplitude and jitter type errors associated with Hermite-type interpolations at equidistant nodes of functions in Paley-Wiener spaces. We give pointwise and uniform estimates. Some examples and comparisons which indicate that applying Hermite interpolations would improve the methods that use the classical sampling theorem are given.

• International Journal of Control, Automation, and Systems
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• v.6 no.2
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• pp.180-185
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• 2008

A new method for relative error continuous and discrete time model order reduction is proposed. The reduction technique is based on two recently developed methods, namely frequency domain balanced truncation within a frequency bound and inner-outer factorization techniques. The proposed method is of interest for practical model order reduction because in this context it shows to keep the accuracy of the approximation as high as possible without sacrificing the computational efficiency. Numerical results show the accuracy and efficiency enhancement of the method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.8C
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• pp.832-837
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• 2005

This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, modified Booth encoder signals (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups (major/minor group) depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that the performance of the proposed method is close to that of the rounding method and much better than that of the truncation method and conventional method. It is also shown that the proposed method leads to up to $28\%\;and\;27\%$ reduction in area and power consumption compared with the ideal squarers, respectively.

• ETRI Journal
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• v.26 no.6
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• pp.657-660
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• 2004

We propose a fine phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine phase tuner presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO using these techniques show that the noise spectrum and mean square error (MSE) for eight output bits of a 3.125 MHz sine waveform are reduced by 8.68 dB and 5.5 dB, respectively, compared to those of the truncation method, and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.129-132
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• 2001

This paper presents an efficient method to estimate the maximum SSN (simultaneous switching noise) for ground interconnection networks in CMOS systems using Taylor's series and analyzes the truncation error that has occurred in Taylor's series approximation. We assume that the curve form of noise voltage on ground interconnection networks is linear and derive a polynomial expression to estimate the maximum value of SSN using $\alpha$-power MOS model. The maximum relative error due to the truncation is shown to be under 1.87% through simulations when we approximate the noise expression in the 3rd-order polynomial.

• Proceedings of the Korean Nuclear Society Conference
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• 2005.10a
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• pp.544-545
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• 2005

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• Bulletin of the Society of Naval Architects of Korea
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• v.19 no.2
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• pp.13-18
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• 1982

The method of Rankine source distribution is emerging as a powerful yet simple alternative for the solution of complicated free surface problems. But it has been uncertain whether the radiation condition could be satisfied exactly by distributing the simple sources on the free surface only. In this paper, it is proved rigorously that the Rankine sources, whose intensities are varying sinusoidally along the axis satisfying the free surface boundary condition, generate the radiation waves both in the infinite and finite-depth flows. A formula is derived to give the upper and lower bounds of the errors in the induced velocity computation that will be introduced by truncating the extent of source distribution on the free surface. Since the truncation is inevitable in the numerical analysis, this formula may be used as a criterion to limit the position of the field points, where velocity computation is made, away from the truncation boundary. A typical analysis shows that the maximum error will be 3.4 percent of the exact induced velocity when the field point is on the free surface two wave lengths away from the truncation boundary.

• Nuclear Engineering and Technology
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• v.20 no.3
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• pp.179-188
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• 1988

A recently developed spatial differencing scheme, Linear Characteristic (LC) scheme is compared with some traditionally used schemes such as Step Difference (SD), Diamond Difference (DD), and Step Characteristic (SC) scheme by analyzing the truncation error calculated numerically in slab geometry. Those four candidate schemes are applied to one simple source sink problem and two criticality problems (one is calculation of multiplication factor and the other is slab critical half thickness). The calculated results are then examined by some equitable measures of error. It is concluded that the LC scheme is terribly more powerful than any other candidate scheme that has been prevalent up to the present time. Moreover, the LC scheme estimates integral parameter such as multiplication factor and critical half thickness much more efficiently than SD or SC scheme. This is due to the fact that the fortuitous error cancellation, which occurs when the deviations of cell average flux are summed over the whole gamut of spatial meshes, happens much more favorably to the LC scheme.