• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.278-278
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• 2016

Solution-processed metal-oxide semiconductors have been considered as the next generation semiconducting materials for transparent and flexible electronics due to their high electrical performance. Moreover, since the oxide semiconductors show high sensitivity to light illumination and possess persistent photoconductivity (PPC), these properties can be utilized in realizing optical memory devices, which can transport information much faster than the electrons. In previous works, metal-oxide semiconductors are utilized as a memory device by using the light (i.e. illumination does the "writing", no-gate bias recovery the "reading" operations) [1]. The key issues for realizing the optical memory devices is to have high photoconductivity and a long life time of free electrons in the oxide semiconductors. However, mono-layered indium-zinc-oxide (IZO) and mono-layered indium-gallium-zinc-oxide (IGZO) have limited photoconductivity and relaxation time of 570 nA, 122 sec, 190 nA and 53 sec, respectively. Here, we boosted up the photoconductivity and relaxation time using a double-layered IZO/IGZO active layer structure. Solution-processed IZO (top) and IGZO (bottom) layers are prepared on a Si/SiO2 wafer and we utilized the conventional thermal annealing method. To investigate the photoconductivity and relaxation time, we exposed 9 mW/cm2 intensity light for 30 sec and the decaying behaviors were evaluated. It was found that the double-layered IZO/IGZO showed high photoconductivity and relaxation time of 28 uA and 1048 sec.

• Applied Chemistry for Engineering
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• v.9 no.1
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• pp.6-12
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• 1998

A FET(Field Effect Transistor) type dissolved $CO_2$ sensor based on Severinghaus type $CO_2$ sensor was fabricated by the photolithographic process. The sensor consists of Ag/AgCl reference electrode and membranes (hydrogel membrane and $CO_2$ gas permeable membrane) on the pH-ISFET base chip. Ag/AgCl reference electrode was fabricated as follows. Ag layer was thermally evaporated and then its upper surface was chemically chloridized into the AgCl. The hydrogel used as an internal electrolyte solution was fabricated by a photolithographic method using 2-hydroxyethyl methacrylate(HEMA) and acrylamide. $CO_2$ permeable membrane on the top of the hydrogel layer was formed by photolithographic process with UV-oligomer. The FET type $pCO_2$ sensor fabricated by photolithographic method showed good linearity within the concentration range of $10^{-3}{\sim}10^0mole/{\ell}$ of dissolved $CO_2$ in aqueous solution with high sensitivity.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.9
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• pp.676-680
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• 2010

In this paper, Fin-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory are fabricated and the electrical characteristics are analyzed. Compared to the planar-type SONOS devices, Fin-type SONOS devices show good short channel effect (SCE) immunity due to the enhanced gate controllability. In memory characteristics such as program/erase speed, endurance and data retention, Fin-type SONOS flash memory are also superior to those of conventional planar-type. In addition, Fin-type SONOS device shows improved SCE immunity in accordance with the decrease of Fin width. This is known to be due to the fully depleted mode operation as the Fin width decreases. In Fin-type, however, the memory characteristic improvement is not shown in narrower Fin width. This is thought to be caused by the Fin structure where the electric field of Fin top can interference with the Fin side electric field and be lowered.

• Journal of the Korean Society of Safety
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• v.33 no.4
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• pp.1-7
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• 2018

This paper is analyzed for the thermal characteristics(1 year) of the 6 components(DC breaker, DC filter(including capacitor and discharge resistance), IGBT(Insulated gate bipolar mode transistor), AC filter, AC breaker, etc.) of a photovoltaic power generation-based PCS(Power conditioning system) below 20 kW. Among the modules, the discharge resistance included in the DC filter indicated the highest heat at $125^{\circ}C$, and such heat resulting from the discharge resistance had an influence on the IGBT installed on the rear side the board. Therefore, risk priority through risk priority number(RPN) of FMEA(Failure modes and effects analysis) sheet is conducted for classification into top 10 %. According to thermal characteristics and FMEA, it is necessary to pay attention to not only the in-house defects found in the IGBT, but also the conductive heat caused by the discharge resistance. Since it is possible that animal, dust and others can be accumulated within the PCS, it is possible that the heat resulting from the discharge resistance may cause fire. Accordingly, there are two options that can be used: installing a heat sink while designing the discharge resistance, and designing the discharge resistance in a structure capable of avoiding heat conduction through setting a separation distance between discharge resistance and IGBT. This data can be used as the data for conducting a comparative analysis of abnormal signals in the process of developing a safety device for solar electricity-based photovoltaic power generation systems, as the data for examining the fire accidents caused by each module, and as the field data for setting component management priorities.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1193-1200
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• 2005

In this paper, we proposed an image hiding method which decreases the amount of calculation encrypting partial data rather than the whole image data using a discrete wavelet transform and a linear scalar quantization which have been adopted as the main technique in JPEG2000 standard and then implemented the proposed algorithm to hardware. A chaotic system was used instead of encryption algorithms to reduce further amount of calculation. It uses a method of random changing method using the chaotic system of the data in a selected subband. For ciphering the quantization index it uses a novel image encryption algorithm of cyclical shifting to the right or left direction and encrypts two quantization assignment method (Top-down coding and Reflection coding), made change of data less. The experiments have been performed with the proposed methods implemented in software for about 500 images. The hardware encryption system was synthesized to find the gate-level circuit with the Samsung $0.35{\mu}m$ Phantom-cell library and timing simulation was performed, which resulted in the stable operation in the frequency above 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.447-457
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• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.783-790
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• 2007

One of the particulars to be considered for providing wireless web service with PC web page is the hardware environment between PC and mobile device. It is because time cost is required in producing mobile contents to suit environment of the connected terminal. Therefore, server side should take account of response time and disk capacity of server. Response time is delayed by content conversion and disk capacity need to store various versions about one content. This paper suggests a pre-service and post-transcoding method to provide faster response time for a mobile terminal. The pre-service is to minimize response time by placing the top priority in servicing contents saved in cache as much as possible even if the quality of contents serviced to mobile terminal may be low. After pre-service is provided, the mobile content is transcoded for the terminal later. Performance level of method proposed was compared through experiment and the result of analysis was described.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.344-348
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• 2007

In this paper, we propose the electrode of the Patterned Vertical Aligned (PVA) cell [1] for high transmittance. We use the 'TechWiz LCD' for calculation of the director configuration and optical characteristics to ensure the results of the proposed electrode structure. In general, the transmittance of the PVA cell depends on the shape of the electrode and cell gap. In this work the width of gate line and data line of the improved electrode design is set to be equal to that of the PVA conventional. Instead, we modified the shape of the top and bottom electrode on order to decrease the area of the defect. For verification, we compared the calculated optical transmittance of the PVA cell with the proposed electrode structure to the conventional PVA cell . As a result, we can confirm that the optical loss due to the variation of the retardation the LC cell around electrode can be definitely decreased by the proposed electrode.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.73-82
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• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.4
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• pp.246-250
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• 2021

TFTs technologies with as high mobility as possible is essential for high-performance large displays. TFTs using nanocrystalline silicon thin films can achieve higher mobility. In this work, the change of the crystalline volume fraction at different hydrogen dilution ratios was investigated by depositing nc-Si:H thin films using PECVD. It was observed that increasing hydrogen dilution ratio increased not only the crystalline volume fraction but also the crystallite size. The thin films with a high crystalline volume fraction (55%) and a low defect density (10¹⁷ cm^-3·eV^-1) were used as top gate TFTs channel layer, leading to a high mobility (55 cm²/V·s). We suggest that TFTs of high mobility to meet the need of display industries can be benefited by the formation of thin film with high crystalline volume fraction as well as low defect density as a channel layer.