• 제목/요약/키워드: timer

검색결과 380건 처리시간 0.026초

기계식 타이머 밸런스 휠의 진동 주파수 측정 및 조정 장비의 개발 (Development of a oscillating frequency measurement and adjustment system of a balance wheel of Mechanical Timer)

  • 이돈진;박수범;안중환
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2000년도 춘계학술대회논문집A
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    • pp.879-883
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    • 2000
  • A system for measuring and adjusting the oscillating frequency of a balance wheel whick determins the accuracy of mechanical timers. The balance wheel oscillates rotatively suspended by a hair spring which is welded at the other end to the pivot tube. The natural oscillatory frequency of the balance wheel is determined by the length of hairspring from the balance wheel to the point if other parameters the length in the torsional oscillation model are not changed, so the frequency of the balance wheel can be adjusted to meet a requirement by the adjustment of the hairspring length using ultrasonic welding. And the movement of wheel teeth is measured in realtime by a high speed photo fiber sensor and Auto Correlation is used to find a more accurate oscillation period from the measured signal with some variations.

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저가형 산업응용 제품을 위한 BLDC 전동기 알고리즘 (BLDC Motor Control Algorithm for Low Cost Industrial Applications)

  • 김남훈;김민회;백원식;최경호;김동희
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2006년도 전력전자학술대회 논문집
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    • pp.155-157
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    • 2006
  • Electrical motors are an integral part of industrial plants with no less than 5 billion motors built word wide every year and the BLDC motor have been increased demand on industrial application. This paper presents BLDC motor control algorithm for cost effective motor application using general purpose microprocessor which have only one on-chip timer and describes how to realize pulse width modulation(PWM) signals with general input/output(I/O) ports to control a three-phase permanent magnet brushless do motor using timer interrupt on MSP430F1232.

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Delay Performance Analysis of the NAK-based SR-ARQ Protocol with the Reverse Acknowledgment (RA) Scheme

  • Han, Je-Chan;Lee, Jai-Yong
    • 한국통신학회논문지
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    • 제33권11B호
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    • pp.989-997
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    • 2008
  • The reverse acknowledgment (RA) scheme supports a fast loss recovery for negative acknowledgment (NAK)-based selective repeat automatic repeat request (SR-ARQ) by detecting a retransmission failure quickly before a retransmission timer expires. In this paper, we evaluate the performance of a NAK-based SR-ARQ protocol with the RA scheme and compare it with the conventional NAK-based SR-ARQ protocol. Particularly, we propose a simple analysis model for the transport delay of the NAK-based SR-ARQ protocol considering the traffic condition, the retransmission persistence, the timer-based retransmissions and the RA scheme's behavior. Both NAK-based SR-ARQ protocols with and without the RA scheme are implemented by using the OPNET simulator. We verified the analysis model's accuracy through the simulation results. Also, we evaluate the performance of the NAK-based SR-ARQ protocol with the RA scheme based on analysis and simulation results.

지능제어를 이용한 Profibus Network의 온라인 성능 관리 (On-line Fuzzy Performance Management of Profibus Networks)

  • 이경창;강송;김태준;이석
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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    • pp.117-117
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    • 2000
  • This paper presents experimental results for peformance management of a Profibus-FMS network. The performance management alms to maintain a uniform level of network performance at all stations under changing network traffic. The performance management algorithm monitors the performance of individual network stations and commands the stations to change their timer values in order to have comparable performance at all stations. In order to determine the amount of timer change, the algorithm employs a set of fuzzy rules. This algorithm has been evaluated on a Profibus network

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조이스틱제어 및 음성으로 제어되는 휠체어의 연구 (Study of the Wheelchair controlled by Joystick and Voices)

  • 민혜정;윤형로
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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    • pp.723-726
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    • 1988
  • This paper is a study about the automatic control of wheelchairs. This is realized by joystick, and is simulated by voice signal recognition. The control system by joystick is designed as follows: joystick paddle is connected with a timer and this timer ouput is high only when the joystick is moved. A computer reads the duration of this high state, and ouputs motor control word decided from this value using look-up table. The control system by voice signal is designed as follows: partial autocorrelation coefficients are computed from A/D converted signals and these values are compared with referance patterns. From this, the motor control word is decided on by the neareast neighbor rule.

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디지털 제어기에 의한 강압형 및 승압형 DC-DC 컨버터의 동시제어 (A Study on the Simultaneous Control of Buck and Boost DC-DC Converter by Digital Controller)

  • 박효식;김희준
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제50권3호
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    • pp.141-146
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    • 2001
  • This paper presents a one digital controller two topology PWM DC-DC converter that controls, simultaneously, the separate Buck converter and boost converter with the different specification by using an inexpensive and efficient 8 bit micro-controller. One timer interrupt is used for the detection of output feedback voltage, and other two timer interrupts are used for the generation of PWM waveform for Buck and Boost converter. The control characteristics of one digital controller two topology PWM DC-DC converter is validated by experimental results.

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실시간 타이머를 적용한 전투체계 SW 설계 방안 (A Study on the Design Method of Combat System SW based on Real-time timer)

  • 박지윤
    • 한국컴퓨터정보학회:학술대회논문집
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    • 한국컴퓨터정보학회 2017년도 제56차 하계학술대회논문집 25권2호
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    • pp.19-20
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    • 2017
  • 전투체계 SW 설계 시 실시간성은 중요하게 고려되어야 할 요소이다. 예로 전투체계 SW 중 하나인 장치관리 모듈은 전투체계를 구성하는 연동단 및 정보처리장치의 운용 상태를 감시하고 상태정보 메시지를 체계관리 모듈에 일정한 주기로 보고하기 위해 실시간성이 요구되어진다. 하지만 장치관리 모듈을 비롯한 전투체계 SW의 운용환경은 실시간성 제공이 어려운 윈도우 운영체제를 사용하고 있다. 또한 전투체계 SW는 재사용성이 높아 멀티 프로세서 환경을 고려하지 않은 설계와 개발 중 추가된 여러기능의 혼재로 실시간성 만족에 어려움이 있다. 이 문제를 해결하기 위해 본 논문에서는 전투체계 SW에 실시간성의 확보를 위한 방안에 대해 연구하였다. 그 방법으로 ms단위의 이벤트 발생이 가능한 실시간 타이머와 CPU 할당을 이용한 쓰레드 스케줄링 방안을 제안하였으며 장치관리 모듈에 적용하였다. 그리고 실험을 통해 성능을 입증하였다. 본 논문에서 제안한 방안은 별도의 상용 솔루션이나 커널 수정이 불가능한 경우 응용 SW 수정으로 실시간성을 높일 수 있다는 장점을 가진다.

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프로그램어블 콘트롤러의 개발 (A Study on development of a Programmable Controller)

  • 김용수;김영현
    • 대한전자공학회논문지
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    • 제20권4호
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    • pp.16-23
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    • 1983
  • 본 논문은 일반적인 제조공정에서 시퀀스 제어용으로 사용될 수 있는 프로그램어블 콘트롤러의 설계제작에 관한 것이다. 본 PC는 Z-8OA마이크로프로세서를 근간으로 하여 하드웨어로는 프로그래밍장치, 입력/출력 모듈, 타이머/퀴운터 모듈과 정전 복구기능 모듈이 제작되었고, 소프트웨어로는 초기상태화 프로그램, 모니터 프로그램, 실행 프로그램 및 정전복구 프로그램이 개발되었다. 특히 한 개의 타이머를 각각 다른 시간 간격으로 여러번 사용할 수 있게 하는 기능과 스캔타임을 줄일 수 있도록 실행 프로그램에 스킵 기능을 새로이 개발하였다.

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액체용 유량계 교정시스템의 Diverter 불확도 특성 연구 (Uncertainty Characteristics of Diverter for Flowmeter Calibration System)

  • 이동근;박종호
    • 한국유체기계학회 논문집
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    • 제11권3호
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    • pp.50-55
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    • 2008
  • The diverter system is a key component in achieving a high accuracy liquid flow rate standard using a static gravimetric system with a flying start and stop method. The diverter is a moving device used to direct flow alternately along its normal course(by pass) or towards the weighing tank. The time needed for collection into the weighing tank is measured using a timer. So it is important to the diversion period is sufficiently fast and triggering point of timer which is determined the filling time. On this studies show that uncertainty of diverter system for changing diversion speed and triggering point was estimated in accordance with Guide to The Expression of Uncertainty in Measurement(ISO).

광시각용 LED 전광판제어 시스템 설계 (A Design of Large Area Viewing LED Panel Control System)

  • 이수범;남상길;조경연;김종진
    • 한국정보처리학회논문지
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    • 제6권5호
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    • pp.1351-1361
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    • 1999
  • The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.

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