• Journal of the Korean Society of Safety
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• v.36 no.2
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• pp.111-119
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• 2021

Multi-dimensional analysis of reactor safety-KINS standard (MARS-KS) is a thermal-hydraulic code to simulate multiple design basis accidents in reactors. The code has been essential to assess nuclear safety, but has mainly focused on light water reactors, which are in the majority in South Korea. Few previous studies considered pressurized heavy water reactor (PHWR) applications. To verify the code applicability for PHWRs, it is necessary to develop MARS-KS input decks under various transient conditions. This study proposes an input model to simulate small-break loss of coolant accidents for PHWRs. The input model includes major equipment and experimental conditions for test B9802. Calculation results for selected variables during steady-state closely follow test data within ±4%. We adopted the Henry-Fauske model to simulate break flow, with coefficients having similar trends to integrated break mass and trip time for the power supply. Transient calculation results for major thermal-hydraulic factors showed good agreement with experimental data, but further study is required to analyze heat transfer and void condensation inside steam generator u-tubes.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.256-259
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• 2003

This paper proposes OPTICAL MARKER fer registering process - one of the 3D measurement process : scan registering - merging - measurement. If the registering work is carried out manually, it can be accompanied with much time and many errors. Because the patterned marker make registering process automatic, many firms use it now. But the physical shape of existing markers is the source of the data loss caused by hiding surface, and the marker arrangement is the source of the time loss. The optical marker proposed in this paper has marker generator, organized a large number of binary coded control laser diode, separate from 3D scan object. So, it does not take much time for the marker disposition, and it is not the origin of the data loss, and the binary coded laser information make the auto-registering possible.

• Journal of Korea Multimedia Society
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• v.8 no.11
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• pp.1556-1564
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• 2005

Various optimization techniques are deployed in the compilation process of a source program for improving the program's execution speed and reducing the size of the source code. Of the optimization pattern matching techniques, the string pattern matching technique involves finding an optimal pattern that corresponds to the intermediate code. However, it is deemed inefficient due to excessive time required for optimized pattern search. The tree matching pattern technique can result in many redundant comparisons for pattern determination, and there is also the disadvantage of high cost involved in constructing a code tree. The objective of this paper is to propose a table-driven code optimizer using the DFA(Deterministic Finite Automata) optimization table to overcome the shortcomings of existing optimization techniques. Unlike other techniques, this is an efficient method of implementing an optimizer that is constructed with the deterministic automata, which determines the final pattern, refuting the pattern selection cost and expediting the pattern search process.

• Journal of KIISE:Software and Applications
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• v.35 no.2
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• pp.59-69
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• 2008

Automatic obfuscation is known to be the most viable method for preventing reverse engineering intentional1y making code more difficult to understand for security purposes. In this paper, we study and implement an obfuscation method for protecting MS Visual C++ programs against attack on the intellectual property in software like reverse engineering attack. That is, the paper describes the implementation of a code obfuscator, a tool which converts a Visual C++ source program into an equivalent one that is much harder to understand. We have used ANTLR parser generator for handling Visual C++ sources, and implemented some obfuscating transformations such as 'Remove comments', 'Scramble identifiers', 'Split variables', 'Fold array', 'Insert class', 'Extend loop condition', 'Add redundant operands', and 'Insert dead code'. We have also evaluated the performance and effectiveness of the obfuscator in terms of potency, resilience, and cost. When the obfuscated source code has been compared with the original source code, it has enough effectiveness for software protection though it incurs some run-time overheads.

• Journal of the Korea Society of Computer and Information
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• v.13 no.3
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• pp.45-55
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• 2008

Due to the increasing complexity of embedded system design, automatic code generation of embedded software and hardware-software co-design methodologies are gaining great interest from industries and academia. Such an automatic design methodologies are always demanding a formal system specification languages for defining designer's idea clearly and precisely. In this paper, we propose automatic embedded C code generation from SDL (Specification and Description Language, ITU-T recommended the SDL as a standard system description language) with considering a real-time uC/OS-II operating system. Our automatic embedded C code generator is expected to provide a fast specification, verification and performance evaluation platform for embedded software designs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.73-79
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• 2007

In this paper the proposed transactor is customized and a generator which roles of automatically generating the transactor according to DUT(Design Under Test)'s input and output is implemented. The customized transactor is designed by rearranging the signals of depending on DUT and transactor protocol which consists of signals of the PCI interface between host computer and FPGA(Field Programmable Gate Array). The implemented automatic generator of transactor generates a Verilog code of transactor by adding DUT's information about input and output ports. Performance and normal working of the generated transactor has been verified by experiments with some verified hardware IPs. Also, an efficiency of the transactor has been verified by comparing with user's manually designed transactor and generated transactor. Moreover, the generator's flexibility has been verified for DUT's information of variable input and output. In case of using the implemented generator, a design time of transactor is reduced.

• Nuclear Engineering and Technology
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• v.27 no.1
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• pp.53-66
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• 1995

Since the current licensed system codes for Non-LOCA safety analysis are applicable only for a specific type PWR, it is necessary to develope a new system analysis code applicable for all apes of PWRs. As a R&D program, KAERI is developing TASS code as an interactive and faster-than-real-time code for the NSSS transient simulation of both CE and Westinghouse plane. It is flexible tool for PWR analysis which gives the user complete control over the simulation through convenient input and output options. In this paper the code applicability to Westinghouse ape plants was verified by comparing the TASS prediction to plant data of loss of AC power and loss of load transients, and comparing to the prediction of RELAP5/MOD3 for feedline break, locked rotor, steam generator tube rupture and steam line break accidents.

• Nuclear Engineering and Technology
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• v.51 no.2
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• pp.402-409
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• 2019

When a loss of coolant accident (LOCA) occurs in a nuclear power plant, accident scenarios which can prevent core damage are defined based on break size. Current probabilistic safety assessment evaluates that core damage can be prevented under small-break LOCA (SBLOCA) and steam generator tube rupture (SGTR) with rapid cool down (RCD) strategy when all safety injection systems are unavailable. However, previous research has pointed out a limitation of RCD in terms of initiation time. Therefore, RCD success criteria estimation based on allowable coping time under a SBLOCA or SGTR when all safety injection systems are unavailable was performed based on time-line and thermal-hydraulic analyses. The time line analysis assumed a single emergency operating procedure flow, and the thermal hydraulic analysis utilized MARS-KS code with variables of break size, cooling rate, and operator allowable time. Results show while RCD is possible under SGTR, it is impossible under SBLOCA at the APR1400's current cooling rate limitation of 55 K/hr. A success criteria map for RCD under SBLOCA is suggested without cooling rate limitation.

• 한국전산유체공학회:학술대회논문집
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• 2009.04a
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• pp.116-120
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• 2009

A two-dimensional unsteady inviscid flow solver has been developed for the simulation of complex geometric configurations on adaptive Cartesian meshes. Embedded condition was used for boundary condition and a predictor-corrector explicit time marching scheme was used for time-accurate numerical simulation. The Cartesian mesh generator, which was previously developed for steady problem, was used grid generation for unsteady flow. The solver was based on ALE formulation for body motion. For diminishing the effects of cut-cells, the cell merging method was used. Using cell merging method, it was eliminated the CFL constraints. The conservation problem, which is caused cell-type variation around region swept by solid boundary, was also solved using cell merging method. The results are presented for 2D circular cylinder and missile launching problem.

• The Journal of Information Technology
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• v.3 no.2
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• pp.13-21
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• 2000

Java native method is proposed for the efficient execution of time-critical code, running of platform dependent job, and reuse of established libraries. If the writing of the Java native method is the speedup of execution time, you must use a compiled language not java language to write native method. Also, you must know the usage of the Java native interface to use native method. To reduce these difficulties, we proposed java native method generator that changes java method into native method automatically. Also, NMG helps programmer to write C implementation for the native method because there Is no need for the concept of JNI.