• Journal of Korean Public Health Nursing
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• v.17 no.1
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• pp.96-112
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• 2003

The purpose of this study was to determine how often toddlers and preschoolers in kindergartens have accidents and what factors affect the accident rate. The study population consisted of 150 children who were attending at nursery schools and 150 children who were attending at kindergartens. The data was collected from ten nursery schools and five kindergartens from five districts in Daegu. The questionnaires were distributed to teachers of participating nursery schools and kindergartens to be completed using nursing care records in the institutions and by interviewing children's parents about all of the accidents happened in a previous year. Data were collected during the period of August 1 through 31, 2002. The results of the study are as follow: 1. Among 300 children, 282 had 506 accidental injuries during the study period. 2. The month, the day and the time with the highest accident rate were April. Monday, and between 2 and 4 o'clock in the afternoon, respectively. 3. Locations where the injury took place most included nursery schools or kindergartens, around the homes of the children, and inside the home. 4. Most accidents were occurred due to lack of carefulness of the children, and the most prevalent forms of injury was abrasions. 5. Most frequently injured part of the body was legs of the children. 6. Most injuries were healed within three days and required first aid measures to disinfect the wound. Mostly, these were performed by family members at home. Some children go to the hospital to suture the open wound. Most frequent type of complication was scar formation and the cost of the treatment ranged from 9,000 to 30,000 won. 7. Children's age. sex, birth order. personality. type of family composition. type of residency. father's occupation, father's age, and mother's age were significantly related to the frequency of injury among children. Children who were in nursery schools and kindergartens need their assessment for accident involving condition according to seasons, time. place. This study provided a very useful and important data to prepare accident prevention education program and accident prevention strategies, and to develop Injury Surveillance System.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.483-492
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• 2013

SURF is an algorithm which extracts feature points and generates their descriptors from input images, and it is being used for many applications such as object recognition, tracking, and constructing panorama pictures. Although SURF is known to be robust to changes of scale, rotation, and view points, it is hard to implement it in real time due to its complex and repetitive computations. Using 3.3 GHz Pentium, in our experiment, it takes 240ms to extract feature points and create descriptors in a VGA image containing about 1,000 feature points, which means that software implementation cannot meet the real time requirement, especially in embedded systems. In this paper, we present a hardware architecture that can compute the SURF algorithm very fast while consuming minimum hardware resources. Two key concepts of our architecture are parallelism (for repetitive computations) and efficient line memory usage (obtained by analyzing memory access patterns). As a result of FPGA synthesis using Xilinx Virtex5LX330, it occupies 101,348 LUTs and 1,367 KB on-chip memory, giving performance of 30 frames per second at 100 MHz clock.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2158-2170
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• 1999

It has been required more reliable communication on processes and improvement of system performance as distributed systems using multicast protocol became widespread. In distributed environment maintaining data consistency through asynchronous execution of processes and coordinating the activities of them would occurs. This paper proposes a total ordering algorithm, TORMP, in order to resolve these problems. TORMP takes advantage of multicast protocol and uses an effective token passing method. It reduces a process delaying time before transmitting its message by multicasting a token simultaneously to every process that initiates the request of the message. Moreover, the processes receiving the token start multicasting the message at the same time, which causes to cut down the overall transmission dely. In case that one process sends a message, TORMP hardly uses the procedure of controlling for ordering. It gives fairly the right of sending messages to all processes in a group with utilizing vector clock. In TORMP, unlike other algorithms, the number of packets generated during ordering process does not depend on the number of processes.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.2
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• pp.74-81
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• 2002

In general, a multipath generator consists of a time delay generator, phase rotator, and amplitude attenuator, and is implemented mostly in an analog manner. Analog, or partially analog versions of a multipath generator is disadvantageous in that they may suffer from problems associated with component aging and adjustment, signal fidelity degradation stemming from repeated A/D and D/A conversion use of high frequency to achieve fine i.e., subsample fractional tin delays. This paper presents the design and implementation methodology of a full digital multipath generator which can be used in performance evaluations of digital terrestrial television as well as communications, receivers. In particular, an efficient practical method is proposed which can achieve both integer and fractional time delays simultaneously, without placing restrictions on the allowable system master clock frequency. The proposed algorithm lends itself to minimizing hardware implementation cost by relegating some fixed put of the computation involved to an IBM PC. The proposed multipath generator occupies only a single digital board space, and its experimental results are provided to corroborate the proposed implementation methodology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1029-1039
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• 2009

In this paper, the existing disparity aquisition algorithms were analyzed, on the bases of which a disparity generation technique that is superior in accuracy to the generation time was proposed. Basically it uses a pixel-by-pixel motion estimation technique. It has a merit of possibility of a high-speed operation. But the motion estimation technique has a disadvantage of lower accuracy because it depends on the similarity of the matching window regardless of the distribution characteristics of the texture in an image. Therefore, an enhanced technique to increase the accuracy of the disparity is required. This paper introduced a variable-sized window matching technique for this requirement. By the proposed technique, high accuracies could be obtained at the homogeneous regions and the object edges. A hardware to generate disparity image was designed, which was optimized to the processing speed so that a high throughput is possible. The hardware was designed by Verilog-HDL and synthesized using Hynix $0.35{\mu}m$ CMOS cell library. The designed hardware was operated stably at 120MHz using Cadence NC-VerilogTM and could process 15 frames per second at this clock frequency.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.479-489
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• 1994

At the present time, it is an important problem that we are to select a transmission line code for the very-high speed optical transmission system which can confidentially transfer the original information signal sequence efficiently, as it is to be the large capacity and the economization for the optical digital transmission system to transfer the information signal sequence at the very-high speed. Therefore, this paper is to select first the proper transmission line codes for the high speed(more than Mb/s) optical transmission system of the proposed two-level unipolar transmission line codes up to date, and to decide a mBIZ (m Binary with One Zero insertion) code as an optimal transmission line code for the very-high speed optical transmission system, resulting from analyzing the performance at the requirements of the transmission line code, such as the maximum consecutive identical digits, the transmission delay time, the increasing rate of clock, the mark rate, the circuit complexity, the supervision of transmission line error, and power spectrum among the selected transmission line codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.914-924
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• 1991

It has been generally used for PLL(Phase Locked Loop) to be synthesized randomly chosen frequency state, but the PLL locking time was inevitable element. A direct digital synthesizer. Which makes output frequency directly in sine wave by a phase accumulating method, could be leiminate the defect, although a phase distortion in frequency spectrum. In order to improve this disadvantage, the phase accumulating method is reconsidered in the side of he output wave formula expression. A new mechanism is proposed, and it is constructed by a most suitable logic elements. The spectrum of synthesized sine waveform is simulated and compared with a measured value, and it’s the coherence frequency hoppong state with the PN(Pseudo Noise) code sequence is confirmed. In this results, the power levels of phase distortion harmonics are decreased to 10~25dB and bandwidths are increased to 420kHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.951-962
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• 2002

A DMT transceiver recovers the sampling time from reserved sub-carriers, the pilots. Since the pilots are available after the FFT, the symbol synchronization must be done before sample synchronization. In DMT VDSL system, symbol synchronization is handled separately from sample synchronization, although the two processes are intimately related. The DMT symbol itself contains sufficient information, the cyclic extension, for symbol synchronization. Using only the sign bit of received signal, the Maximum Likelihood Estimation solution is derived. The Tx windowing in the transmitter of DMT VDSL system results in the blurring of MLE peaks. We propose the weighted summing MLE method using the sign bit which produces the clearly sharp top of MLE peaks. The stability of symbol synchronization is improved significantly by averaging over a few symbols. This paper presents the study of the original MLE and the weighted summing MLE using sign bit. A clock difference between transmitter and receiver destroys the oahogonality of the carriers. Therefore, a receiver using asynchronous sampling must perform timing correction in the discrete-time domain. We introduce an efficient digital sample synchronization method which is based on temporal and frequency domain digital signal processing.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1900-1906
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• 1997

In this paper, the efficient BILBO(named EBILBO) is designed for BIST that is able to batch the testing when circuit is designed on FPGA. The proposed algorithm of batch testing is able to test the normal operation speed with one-pin-count that can control all part of large and complex circuit. PRTPG is used for the test pattern and MISR is used for PSA. The proposed algorithm of batch testing is VHDL coding on behavioral description, so it is easily modified the model of test pattern generation, signature analysis and compression. The EBILBO's area and the performance of designed BIST are evaluated with ISCAS89 benchmark circuit on FPGA. In circuit with above 600 cells, it is shown that area is reduced below 30%, test pattern is flexibly generated about 500K and the fault coverage is from 88.3% to 100%. EBILBO for the proposed batch testing BIST is able to execute concurrently normal and test mode operation in real time to the number of $s+n+(2^s/2^p-1)$ clock(where, in CUT, # of PI;n, # of register, p is order # of polynomial). The proposed algorithm coded with VHDL is made of library, then it well be widely applied to DFT that satisfy the design and test field on sme time.