• 한국자기학회:학술대회 개요집
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• 한국자기학회 2010년도 임시총회 및 하계학술연구발표회
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• pp.79-79
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• 2010

Semimetallic bismuth (Bi) has been extensively investigated over the last decade since it exhibits very intriguing transport properties due to their highly anisotropic Fermi surface, low carrier concentration, long carrier mean free path l, and small effective carrier mass $m^*$. In particular, the great interest in Bi nanowires lies in the development of nanowire fabrication methods and the opportunity for exploring novel low-dimensional phenomena as well as practical application such as thermoelectricity[1]. In this work, we introduce a self-assembled interconnection of nanostructures produced by an on-film formation of nanowires (OFF-ON) method in order to form a highly ohmic Bi nanobridge. A Bi thin film was first deposited on a thermally oxidized Si (100) substrate at a rate of $40\;{\AA}/s$ by radio frequency (RF) sputtering at 300 K. The sputter system was kept in an ultra high vacuum (UHV) of $10^{-6}$ Torr before deposition, and sputtering was performed under an Ar gas pressure of 2m Torr for 180s. For the lateral growth of Bi nanowires, we sputtered a thin Cr (or $SiO_2$) layer on top of the Bi film. The Bi thin films were subsequently put into a custom-made vacuum furnace for thermal annealing to grow Bi nanowires by the OFF-ON method. After thermal annealing, the Bi nanowires cannot be pushed out from the topside of the Bi films due to the Cr (or $SiO_2$) layer. Instead, Bi nanowires grow laterally as a mean s of releasing the compressive stress. We fabricated a self-assembled Bi nanobridge (d=192 nm) device in-situ using OFF-ON through annealing at $250^{\circ}C$ for 10hours. From I-V measurements taken on the Bi nanobridge device, contacts to the nanobridge were found highly ohmic. The quality of the Bi nanobridge was also proved by the high MR of 123% obtained from transverse MR measurements. These results manifest the possibility of self-assembled nanowire interconnection between various nanostructures for a variety of applications and provide a simple device fabrication method to investigate transport properties on nanowires without complex patterning and etching processes.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.321-322
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• 2007

In order to increase the cost effectiveness of solar cells, module production should be treated more comprehensively. Back contact cells offer distinct advantage in the interconnection of cells to modules. Thereby Mo thin film were prepared in order to clarify optimum conditions for growth of the thin film depending upon process, and then by changing a number of deposition conditions and substrate temperature conditions variously, structural and electrical characteristics were measured. For the manufacture of the Mo were vapor-deposited in the named order. Among them, Mo were vapor-deposited by using the sputtering method in consideration of their adhesive force to the substrate, and the DC power was controlled so that the composition of Mo, while the surface temperature having an effect on the quality of the thin film was changed from R.T$[^{\circ}C]$ to $200[^{\circ}C]$ at intervals of $50[^{\circ}C]$. Micro-structural studies were carried out by XRD (D/MAX-1200, Rigaku Co.) and SEM (JSM-5400, Jeol Co.). Electrical properties were measured by CMT-SR3000 Measurement System.

• 한국재료학회지
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• 제19권7호
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• pp.349-355
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• 2009

Metal thin film patterns on a LTCC substrate, which was connected through inner via and metal paste for electrical signals, were formed by a screen printing process that used electric paste, such as silver and copper, in a conventional method. This method brought about many problems, such as non uniform thickness in printing, large line spaces, and non-clearance. As a result of these problems, it was very difficult to perform fine and high resolution for high frequency signals. In this study, the electric signal patterns were formed with the sputtered metal thin films (Ti, Cu) on an LTCC substrate that was coated with protective oxide layers, such as $TiO_2$ and $SiO_2$. These electric signal patterns' morphology, surface bonding strength, and effect on electro plating were also investigated. After putting a sold ball on the sputtered metal thin films, their adhesion strength on the LTCC substrate was also evaluated. The protective oxide layers were found to play important roles in creating a strong design for electric components and integrating circuit modules in high frequency ranges.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.72-73
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• 2005

Stress behavior was studied to investigate the internal behaviors of boron, carbon, and nitrogen in the 1000${\AA}$-thick tungsten boron carbon nitride (W-B-C-N) thin films. The impurities in the W-B-C-N thin films provide stuffing effects that were very effective for preventing the interdiffusion between interconnection metal and silicon substrate during the subsequent high temperature annealing process. The resistivity of W-B-C-N thin film decreases as an annealing temperature increase. The W-B-C-N thin films have compressive stress, and the stress value decreased up to $4.11\times10^{10}dyne/cm^2$ as an $N_2$ flow rate increases up to 3 sccm.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.456-459
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• 2002

This paper describes fabrication and characteristics of ceramic pressure sensor for working at high temperature. The proposed pressure sensor consists of a Ta-N thin-film, patterned on a Wheatstone bridge configuration, sputter deposited onto thermally oxidized Si membranes with an aluminium interconnection layer. The fabricated pressure sensor presents a low temperature coefficient of resistance, high sensitivity, low non-linearity and excellent temperature stability. The sensitivity is 1.097~1.21mV/$V{\cdot}kgf/cm^2$ in the temperature range of $25{\sim}200^{\circ}C$ and the maximum non-linearity is 0.43 %FS.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.587-590
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• 2000

This paper presents the characteristics of metal thin-film pressure sensors. The micro pressure sensors consists of a chrom thin-film, patterned on a Wheatstone bridge configuration, sputter-deposited onto thermally oxidized Si wafer an aluminium interconnection layer. The fabricated micro pressure sensors shows a low temperature coefficient of resistance, high-sensitivity, low non-linearity and excellent temperature stability. The sensitivity is 1.16~1.21 mV/V.kgf/$\textrm{cm}^2$ in the temperature range of 25~l0$0^{\circ}C$ and the maximum non-linearity is 0.21 %FS.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.178-178
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• 2010

With the scaling down of ULSI(Ultra Large Scale Integration) circuit of CMOS(Complementary Metal Oxide Semiconductor)based electronic devices, the electronic devices become more faster and smaller size that are promising field of semiconductor market. However, very narrow line width has some disadvantages. For example, because of narrow line width, deposition of conformal and thin barrier is difficult. Besides, proportion of barrier width is large, thus resistance is high. Conventional PVD(Physical Vapor Deposition) thin films are not able to gain a good quality and conformal layer. Hence, in order to get over these side effects, deposition of thin layer used of ALD(Atomic Layer Deposition) is important factor. Furthermore, it is essential that copper atomic diffusion into dielectric layer such as silicon oxide and hafnium oxide. If copper line is not surrounded by diffusion barrier, it cause the leakage current and devices degradation. There are some possible methods for improving the these secondary effects. In this study, TaNx, is used of Tertiarybutylimido tris (ethylamethlamino) tantalum (TBITEMAT), was deposited on the 24nm sized trench silicon oxide/silicon bi-layer substrate with good step coverage and high quality film using plasma enhanced atomic layer deposition (PEALD). And then copper was deposited on TaNx barrier using same deposition method. The thickness of TaNx was 4~5 nm. TaNx film was deposited the condition of under $300^{\circ}C$ and copper deposition temperature was under $120^{\circ}C$, and feeding time of TaNx and copper were 5 seconds and 5 seconds, relatively. Purge time of TaNx and copper films were 10 seconds and 6 seconds, relatively. XRD, TEM, AFM, I-V measurement(for testing leakage current and stability) were used to analyze this work. With this work, thin barrier layer(4~5nm) with deposited PEALD has good step coverage and good thermal stability. So the barrier properties of PEALD TaNx film are desirable for copper interconnection.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.243.2-243.2
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• 2016

Tungsten (W) is recently gaining attention as a potential candidate to replace Cu in semiconductor metallization due to its expected improvement in material reliability and reduced resistivity size effect. In this study, the impact of electron scattering at grain boundaries in a polycrystalline W thin film was investigated. Two nominally 300 nm-thick films, a (110)-oriented single crystal film and a (110)-textured polycrystalline W film, were prepared onto (11-20) Al2O3 substrate and thermally oxidized Si substrate, respectively in identical fabrication conditions. The lateral grain size for the polycrystalline film was determined to be $119{\pm}7nm$ by TEM-based orientation mapping technique. The film thickness was chosen to significantly exceed the electron mean free path in W (16.1 and 77.7 nm at 293 and 4.2 K, respectively), which allows the impact of surface scattering on film resistivity to be negligible. Then, the difference in the resistivity of the two films can be attributed to grain boundary scattering. quantitative analyses were performed by employing the Mayadas-Shatzkes (MS) model, where the grain boundary reflection coefficient was determined to be $0.42{\pm}0.02$ and $0.40{\pm}0.02$ at 293 K and 4.2 K, respectively.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권4호
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• pp.173-178
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• 2003

In this paper, we studied the physical and electrical characteristics of $\textrm{WSi}_{x}$ thin film with respect to the adoption of the DCS (dichlorosiliane) post flow and the variation of deposition temperature. XRD measurements show that as deposited thin film has a hexagonal structure regardless of deposition Process. However, we find that the phase of thin film has changed to a tetragonal structure after the heat treatment at $680^{\circ}C$. Adoption of DCS post flow and increment of deposition temperature result in the increments of Si/W composition ratio. These conditions also result in the increment of sheet resistance by the amount 3.0~4.2$\Omega$/$\square$, but give the tendency in the decrement of stress by 0.27~0.3 E10dyne/$\textrm{cm}^2$. We also find that the contact resistance of word line and bit line interconnection was decreased by the amount 5.33~16.43$\mu$$\Omega$-$\textrm{cm}^2$, when applying DCS post flow and increasing deposition temperature.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.