• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.1-7
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• 2006

WLCSP(wafer level chip size package)는 웨이퍼 레벨에서 패키지 공정이 이루어지는 차세대 패키지 중 하나이다. WLCSP는 웨이퍼 레벨에서 패키지 공정이 이루어진다는 특징으로 인하여 웨이퍼당 생산되는 반도체 칩의 수에 따라 그 패키징 비용을 크게 줄일 수 있다는 장점이 있다. 그러나 응력 버퍼 역할을 하는 기판을 없애는 혁신적인 구조로 인하여 솔더 조인트의 신뢰성이 기존의 BGA 패키지에 비하여 취약하게 되는데, 이러한 솔더 조인트 신뢰성에 대하여 반도체 칩과 솔더볼을 연결하는 폴리머 절연층은 열팽창계수 차이에 의해 발생하는 응력을 흡수하는 중요한 역할을 하게 된다. 본 연구에서는 하이닉스에서 개발한 Omega-CSP를 사용하여 솔더볼 배열 변화와 제 1 절연층의 특성에 따른 솔더 조인트의 열피로 특성을 평가하였다. 그 결과 절연층의 특성 변화가 솔더 조인트의 열피로 특성에 주는 영향은 솔더볼 배열 구조에 따라 변화되는 것을 확인하였다.

• Journal of Welding and Joining
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• 제32권3호
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• pp.74-80
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• 2014

Due to environmental regulations (RoHS, WEEE and ELV) of the European Union, electronics and automotive electronics have to eliminate toxic substance from their devices and system. Especially, reliability issue of lead-free solder joint is increasing in car electronics due to ELV (End-of-Life Vehicle) banning from 2016. We have prepared engine control unit (ECU) modules soldered with Sn-40Pb and Sn-3.0Ag-0.5Cu (SAC305) solders, respectively. Degradation characteristics of solder joint strength were compared with various conditions of automobile environment such as cabin and engine room. Thermal cycle test (TC, $-40^{\circ}C$ ~ ($85^{\circ}C$ and $125^{\circ}C$), 1500 cycles) were conducted with automotive company standard. To compare shear strength degradation rate with eutectic and Pb-free solder alloy, we measured shear strength of chip components and its size from cabin and engine ECU modules. Based on the TC test results, finally, we have known the difference of degradation level with solder alloys and use environmental conditions. Solder joints degradation rate of engine room ECU is superior to cabin ECU due to large CTE (coefficient of thermal expansion) mismatch in field condition. Degradation rate of engine room ECU is 50~60% larger than cabin room electronics.

• 한국초전도ㆍ저온공학회논문지
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• 제16권4호
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• pp.49-52
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• 2014

REBCO coated conductor (CC) tapes with superior mechanical and electromechanical properties are preferable in applications such as superconducting coils and magnets. The CC tapes should withstand factors that can affect their performance during fabrication and operation of its applications. In coil applications, CC tapes experience different mechanical constraints such as tensile or compressive stresses. Recently, the critical current ($I_c$) degradation of CC tapes used in coil applications due to delamination were already reported. Thermal cycling, coefficient of thermal expansion mismatch among constituent layers, screening current, etc. can induce excessive transverse tensile stresses that might lead to the degradation of $I_c$ in the CC tapes. Also, CC tapes might be subjected to very high magnetic fields that induce strong Lorentz force which possibly affects its performance in coil applications. Hence, investigation on the delamination mechanism of the CC tapes is very important in coiling, cooling, operation and design of prospect applications. In this study, the electromechanical properties of REBCO CC tapes fabricated by reactive co-evaporation by deposition and reaction (RCE-DR) under transversely applied loading were investigated. Delamination strength of the CC tape was determined using the anvil test. The $I_c$ degraded earlier under transverse tensile stress as compared to that under compressive one.

• 한국전기전자재료학회논문지
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• 제26권1호
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• pp.64-67
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• 2013

$Fe_3O_4$(magnetite) having half metallic property attracts great attention material with high curie temperature in spintronics. $Fe_3O_4$ thin films and nanowires were grown onto c-$Al_2O_3$(0001) at various substrate temperatures. $Fe_3O_4$ films deposited from 300 to $600^{\circ}C$ are influenced by thermal stress induced from mismatch of thermal expansion coefficient between $Fe_3O_4$ and $Al_2O_3$ (0001) substrate. The $Fe_3O_4$ nanowires grown at $640^{\circ}C$ showed a diameter of 130 nm and a length of $2-10{\mu}m$. The nanowire arrays fabricated by pulsed laser deposition technique have high coercivity($H_c$) of 608 Oe and Squareness($M_r/M_s$) of 0.68 in perpendicular direction.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.112-112
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• 2009

In this study, the effect of a long post-deposition thermal annealing(600 and 1000 $^{\circ}C$) on the surface acoustic wave (SAW) properties of polycrystalline (poly) aluminum-nitride (AlN) thin films grown on a 3C-SiC buffer layer was investigates. The poly-AlN thin films with a (0002) preferred orientation were deposited on the substrates by using a pulsed reactive magnetron sputtering system. Experimental results show that the texture degree of AlN thin film was reduced along the increase in annealing temperature, which caused the decrease in the electromechanical coupling coefficient ($k^2$). The SAW velocity also was decreased slightly by the increase in root mean square (RMS) roughness over annealing temperature. However, the residual stress in films almost was not affect by thermal annealing process due to small lattice mismatch different and similar coefficient temperature expansion (CTE) between AlN and 3C-SiC. After the AlN film annealed at 1000 $^{\circ}C$, the insertion loss of an $IDT/AlN/3C-SiC/SiO_2/Si$ structure (-16.44 dB) was reduced by 8.79 dB in comparison with that of the as-deposited film (-25.23 dB). The improvement in the insertion loss of the film was fined according to the decrease in the grain size. The characteristics of AlN thin films were also evaluated using Fourier transform-infrared spectroscopy (FT-IR) spectra and X-ray diffraction (XRD), scanning electron microscopy (SEM), and atomic force microscopy (AFM) images.

• Macromolecular Research
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• 제12권1호
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• pp.78-84
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• 2004

Advanced epoxy molding compounds (EMCs) should be considered to alleviate the thermal stress problems caused by low thermal conductivity and high elastic modulus of an EMC and by the mismatch of the coefficient of thermal expansion (CTE) between an EMC and the Si-wafer. Though A1N has some advantages, such as high thermal conductivity and mechanical strength, an A1N-filled EMC could not be applied to commercial products because of its low fluidity and high modules. To solve this problem, we used 2-$\mu\textrm{m}$ fused silica, which has low porosity and spherical shape, as a small size filler in the binary mixture of fillers. When the composition of the silica in the binary filler system reached 0.3, the fluidity of EMC was improved more than twofold and the mechanical strength was improved 1.5 times, relative to the 23-$\mu\textrm{m}$ A1N-filled EMC. In addition, the values of the elastic modules and the dielectric constant were reduced to 90％, although the thermal conductivity of EMC was reduced from 4.3 to 2.5 W/m-K, when compared with the 23-$\mu\textrm{m}$ A1N-filled EMC. Thus, the A1N/silica (7/3)-filled EMC effectively meets the requirements of an advanced electronic packaging material for commercial products, such as high thermal conductivity (more than 2 W/m-K), high fluidity, low elastic modules, low dielectric constant, and low CTE.

• 마이크로전자및패키징학회지
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• 제21권3호
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• pp.7-17
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• 2014

Power electronics modules are semiconductor components that are widely used in airplanes, trains, automobiles, and energy generation and conversion facilities. In particular, insulated gate bipolar transistors(IGBT) have been widely utilized in high power and fast switching applications for power management including power supplies, uninterruptible power systems, and AC/DC converters. In these days, IGBT are the predominant power semiconductors for high current applications in electrical and hybrid vehicles application. In these application environments, the physical conditions are often severe with strong electric currents, high voltage, high temperature, high humidity, and vibrations. Therefore, IGBT module packages involves a number of challenges for the design engineer in terms of reliability. Thermal and thermal-mechanical management are critical for power electronics modules. The failure mechanisms that limit the number of power cycles are caused by the coefficient of thermal expansion mismatch between the materials used in the IGBT modules. All interfaces in the module could be locations for potential failures. Therefore, a proper thermal design where the temperature does not exceed an allowable limit of the devices has been a key factor in developing IGBT modules. In this paper, we discussed the effects of various package materials on heat dissipation and thermal management, as well as recent technology of the new package materials.

• 한국세라믹학회지
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• 제51권3호
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• pp.170-176
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• 2014

Effective glass frit compositions enabled to absorb laser energy, and to seal a commercial dye-sensitized solar-cell-panel substrate were developed by using $V_2O_5$-based glasses with various amounts of $TeO_2$ substitution. The latter was intended to increase the lifetime of the solar cells. Substitution of $V_2O_5$ by $TeO_2$ provided a strong network structure for the glasses via the formation of tetrahedral pyramids in the glass, and changed the various glass properties, such as glass transition temperature ($T_g$), dilatometric softening point ($T_d$), crystallization temperature, coefficient of thermal expansion (CTE), and glass flowage without any detrimental effect on the laser absorption property of the glasses. The thermal expansion mismatch (${\Delta}{\alpha}$) between the glass frit and the substrate could be controlled within less than ${\pm}5%$ by addition of 10 wt% of ${\beta}$-eucryptite. An 810 nm diode laser was used for the sealing test. The laser sealing test revealed that the VZBT20 glass frit with 10 wt% ${\beta}$-eucryptite was successfully sealed the substrates without interfacial cracks and pores. The optimum sealing conditions were provided by a beam size of 3 mm, laser power of 40 watt, scan speed of 300 mm/s, and 200 irradiation cycles.

• 한국재료학회지
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• 제9권6호
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• pp.599-603
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• 1999

AIN과 저온 GaN 완충충율 이용하여 Si 기판 위의 후막 GaN의 성장특성을 조샤하였다. Si과 GaN의 격자부정합도와 열팽창계수의 차이를 줄이기 위해 AIN과 저온 GaN를 완충충으로 사용하였다. AIN은 RF sputter를 이용하여 중착온도와 증착시간 및 RF power에 따른 표면 거칠기를 AFM으로 조사하여 최척조건을 확립하여 사용하였다. 또한 저온에서 GaN를 성장시켜 이를 완충충으로 이용하여 후막 GaN의 성장시 미치는 영향을 살펴보았다. 성장온도와 V/III 비율이 후막 성장시 표면특성과 결정성 및 성장속도에 미치는 영향을 조사하였다. 후막 GaN의 표연특성 및 막의 두께는 SEM과 $\alpha-step$을 이용하여 측정하였으며 결정성은 X-ray Diffractometer를 이용하여 조사하였다.