• Journal of Korean Society for Atmospheric Environment
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• v.16 no.4
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• pp.363-372
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• 2000

In order to overtake a quantitative analysis of effect of anthropogenic heat and different land-use on urban thermal environment numerical simulation of surface energy budget was carried out under typical summer synoptic condition. It is beneficial to understand surface temperature of complex urban surace. The different land-use types are classified of rice field farm fruit garden residential region forest water and swamp by using map scaled 1/25000 of Pusan metropolitan. The model predicts that maximum heat island intensity in the central part of Pusan is 7$^{\circ}C$ at 2000 LST in summertime. The surface temperature is propotional to the density of constructions. The effect of anthropogenic heat generation on surface temperature is the increase of 0.3$^{\circ}C$ at 1400LST in the central part of Pusan during summertime.

• Journal of Environmental Science International
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• v.24 no.6
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• pp.819-826
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• 2015

This study measured temperatures and albedos of urban surfaces for different colors and materials during summer, and calculated the energy budget over different urban surfaces to find out the thermal performance affecting the heat built-up. The study selected six surface colors and 13 materials common in urban landscape. Their surface temperatures (Ts) and albedos were measured at a given time interval in the daytime from June to August. Average Ts over summer season for asphalt-colored brick was $4.0^{\circ}C$ higher than that for light red-colored one and $9.7^{\circ}C$ higher than that for white-colored one. The Ts for artificial surface materials of asphalt paving, brown brick wall, and green concrete wall was $6.0^{\circ}C$ higher than that for natural and semi-natural ones of grass, grassy block, and planted concrete wall. There was the greatest difference of $16.3^{\circ}C$ at midafternoon in the Ts between asphalt paving and planted concrete wall. Average albedo over summer season of surface materials ranged from 0.08 for asphalt paving to 0.67 for white concrete wall. This difference in the albedo was associated with a maximum of $15.7^{\circ}C$ difference at midafternoon in the Ts. Increasing the albedo by 0.1 (from 0.22 to 0.32) reduced the Ts by about $1.3^{\circ}C$. Average storage heat at midday by natural and semi-natural surfaces of grass and grassy block was about 10% lower than that by artificial ones of asphalt, light-red brick, and concrete. Reflected radiation, which ultimately contributes to heating the urban atmosphere, was 3.7 times greater for light-red brick and concrete surfaces than for asphalt surface. Thus, surfaces with in-between tone and color are more effective than dark- or white-colored ones, and natural or semi-natural surfaces are much greater than artificial ones in improving the urban thermal environment. This study provides new information on correlation between Ts and air temperature, relationship between albedo and Ts, and the energy budget.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.43-47
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• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• Journal of the Korean Vacuum Society
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• v.12 no.3
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• pp.168-173
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• 2003

Recently, according to the rapid progress in Flat-panel-display industry, there has been a growing interest in the poly-Si process. Compared with a-Si, poly-Si offers significantly high carrier mobility, so it has many advantages to high response rate in Thin Film Transistors (TFT's). We have investigated a new process for the high temperature Solid Phase Crystallization (SPC) of a-Si films without any damages on glass substrates using thin film heater. because the thin film heater annealing method is a very rapid thermal process, it has very low thermal budget compared to the conventional furnace annealing. therefore it has some characteristics such as selective area crystallization, high temperature annealing using glass substrates. A 500 $\AA$-thick a-Si film was crystallized by the heat transferred from the resistively heated thin film heaters through $SiO_2$ intermediate layer. a 1000 $\AA$-thick $TiSi_2$ thin film confined to have 15 $\textrm{mm}^{-1}$ length and various line width from 200 to 400 $\mu\textrm{m}$ was used as the thin film heater. By this method, we successfully crystallized 500 $\AA$-thick a-Si thin films at a high temperature estimated above $850^{\circ}C$ in a few seconds without any thermal deformation of g1ass substrates. These surprising results were due to the very small thermal budget of the thin film heaters and rapid thermal behavior such as fast heating and cooling. Moreover, we investigated the time dependency of the SPC of a-Si films by observing the crystallization phenomena at every 20 seconds during annealing process. We suggests the individual managements of nucleation and grain growth steps of poly-Si in SPC of a-Si with the precise control of annealing temperature. In conclusion, we show the SPC of a-Si by the thin film heaters and many advantages of the thin film heater annealing over other processes

• Atmosphere
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• v.18 no.2
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• pp.137-146
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• 2008

This study examines one thermal index, perceived temperature (PT), over the Korean Peninsula during 2007 summer. Heat/cold stress has been described using air temperature and humidity for warm seasons and air temperature and wind velocity in the cold conditions, while PT is based on a heat budget model of the human body that considers air temperature, humidity, wind velocity and radiation effect regardless of climates, regions and seasons. PT is higher about $4-5^{\circ}C$ than air temperature in the summer. Humidity increases PT, while wind tends to reduces PT possibly by evaporation of water vapor. The geographical distribution of summer PT indicates that the lowest PT happened in the east central region, with the appearance of the highest PT in the inland of southern region in Korea. Although the latitudinal trend shows that PT decreases northward, inland PT is higher than that of coastal region. Compared to the heat index or the discomfort index that considers air temperature and humidity, PT represents distinctive regional characteristics of thermal comfort. The distribution of PT shows that it may be a useful thermal index for the assessment of thermal comfort or stress region in the Korean Peninsula.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of computational fluids engineering
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• v.12 no.3
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• pp.62-68
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• 2007

A conceptual thermal design is performed for the optical payload system of a geostationary satellite. The optical payload considered in this paper is GOCI(Geostationary Ocean Color Imager) of COMS of Korea. The radiative thermal control system is employed in order to expect a small thermal gradient in the telescope structure of GOCl. Two design margins are applied to the dedicated radiator dimensioning, and three kinds of configuration to the heater power sizing. A Monte-Carlo ray tracing method and a network analysis method are utilized to calculate radiative couplings and thermal responses respectively. At the level of conceptual design, sizing thresholds are presented for the radiator and heater on the purpose of determining the mass and power budget of the spacecraft.

• Proceedings of the Materials Research Society of Korea Conference
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• 1997.05a
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• pp.18-18
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• 1997

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.125-125
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• 2003

PZT(Pb(Zr,Ti)O3)는 우수한 강유전 특성을 가지기 때문에 FRAM (Ferroelectric Random Access Memory) 소자에 응용하기 위해 많은 연구가 진행되고 있다. 스퍼터에 의해 증착된 PZT는 처음에 pyrochlore상으로 존재하다가 후 열처리를 통해 이력 특성을 나타내는 perovskite상으로 천이된다. 일반적인 furnace열처리 방법은 고온에서의 장시간 열처리가 요구되고 Pb-loss현상이나 TiO2와 같은 이차상의 생성 그리고 하부 Pt전극의 roughness증가 및 crack과 같은 문제점이 있다. 최근 들어 후 열처리를 RTA로 이용하는 연구가 진행되고 있는데 이는 열처리 시간이 짧기 때문에 위와 같은 문제점을 개선할 수 있었다. 하지만 RTA방법 또한 어느 정도의 thermal budget이 존재하고 추가적 장비가 필요하며 기판의 전체적 가열공정이므로 다른 CMOS공정과 compatibility가 떨어진다. 따라서 본 실험에서는 위와 같은 문제를 해결하고자 노력을 집중하였고 이를 위한 새로운 열처리 방법을 개발하였다. 즉 Pt 하부전극에 전압(전류)을 인가하여 순간적으로 고온으로 결정화시키는 새로운 공정을 모색하였는데 이와 같은 방법은 열처리를 위한 추가적인 장비가 필요없고 국부적으로 순간적인 가열이기 때문에 glass기판에도 적합하며 RTA보다 승온시간 및 열처리 시간이 짧기 때문에 thermal budget도 줄일 수 있었다.