• Title/Summary/Keyword: test circuit

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Robust Test Generation for Stuck-Open Faults in CMOS Circuits (CMOS 회로의 Stuck-open 고장검출을 위한 로보스트 테스트 생성)

  • Jung, Jun-Mo;Lim, In-Chil
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.11
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    • pp.42-48
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    • 1990
  • In this paper robust test generation for stuck-open faults in CMOS circuits is proposed. By obtaining initialization patterns and test patterns using the relationship of bit position and Hamming weight among input vectors for CMOS circuit test generation time for stuck-open faults can be reduced, and the problem of input transition skew which make fault detection difficult is solved, and the number of test sequences are minimized. Also the number of test sequences is reduced by arranging test sequences using Hamming distance between initialization patterns and test patterns for circuit.

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A Study on the Characteristics Assessment and Fabrication of Distribution Board according to KEMC Standards (KEMC 규정에 의한 분전반의 제작 및 특성 평가에 관한 연구)

  • Lee, Byung-Seol;Choi, Chung-Seog
    • Fire Science and Engineering
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    • v.31 no.3
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    • pp.63-72
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    • 2017
  • This study fabricated a low-voltage 10 circuit distribution board based on the KEMC (Korea Electrical Manufacturers Cooperative) 2102-610 standard and performed a characteristics assessment of the developed 10 circuit distribution board to secure product stability. The developed 10 circuit distribution board is designed to have the characteristics of insulation materials, as well as resistance to corrosion ultraviolet radiation and mechanical impact. The developed distribution board is fabricated to have an appropriate protection class of enclosure, electric shock prevention and protection circuits, switchgear and its components, internal electrical circuits and connectors, external conduct terminal, insulation characteristics, temperature rise test, heat resistance, etc. The developed 10 circuit distribution board consists of a single phase circuit and 3-phase circuits. It is possible to measure in real time the leakage current generated from the load distribution line by installing a sensor module at the load side of each of the branched switchgears. In addition, it is possible to increase a circuit according to the use and purpose of the load and to also manage and check the load in real time. Temperature rise tests were performed on the developed 10 circuit distribution board at 18 places including the inlet connection, main circuit and distribution circuit bus bars and bus bar supports, etc. The highest temperature of $65.3^{\circ}C$ was measured at the R-Phase of the connection of the MCCB power supply for the branch circuit bus bar and a temperature rise of $61.6^{\circ}C$ was measured at the T-Phase of the load side. When applying thermal stress to an MCCB for 6 hours at $180^{\circ}C$ using a heat resistant experimental device, it was found that the actuator lever was transformed and moved in the tripped state.

Test Methodology for Multiple Clocks Single Capture Scan Design based on JTAG IEEE1149.1 Standard (IEEE 1149.1 표준에 근거한 다중 클럭을 이용한 단일 캡쳐 스캔 설계에 적용되는 경계 주사 테스트 기법에 관한 연구)

  • Kim, In-Soo;Min, Hyoung-Bok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.5
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    • pp.980-986
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    • 2007
  • Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.

Understanding the Principles of Wheatstone Bridge Circuit (휘트스톤 브리지 회로의 원리에 대한 이해)

  • Choi, Byung-Hee;Ryu, Chang-Ha
    • Explosives and Blasting
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    • v.35 no.2
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    • pp.9-17
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    • 2017
  • The Wheatstone bridge is an important electrical circuit that is widely used to measure extremely small resistance changes in strain gages. The strain gages are attached to the structure or specimen whose deformation is to be detected. The Wheatstone bridge finds one of its major applications in the areas of static and dynamic strength tests for various engineering materials. In the split Hopkinson pressure bar (SHPB) system, for example, the bridge circuit is required to measure the dynamic strains of the incident and transmitted bars along which the stress wave propagates. In this article, the principles of the Wheatstone bridge circuit are in detail explained for easy reference during laboratory experiments associated with rock dynamics. Especially, the circuit arrangements of the quater, half, and full bridges are presented with their basic uses.

Evaluation Method I of the Small Current Breaking Performance for SF(sub)6-Blown High-Voltage Gas Circuit Breakers (초고압 $SF_6$ 가스차단기의 소전류 차단성능 해석기술 I)

  • 송기동;이병운;박경엽;박정후
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.50 no.7
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    • pp.331-337
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    • 2001
  • With the increasing reliability of analysis schemes and the dramatically increased calculating speed, the computer simulation has become and indispensable process to predict the interruption capacity of circuit breakers. Generally, circuit breakers have to possess both the small current and large current interruption abilities and the circuit breaker designers need to evaluate its capacities to save the time and the expense. The analysis of small current and the large current interruption performances have been considered separately because the phenomena occurring in a interrupter are quite different. To analyze the dielectric recovery after large current interruption many physical phenomena such as heat transfer, convection and arc radiation, the nozzle ablation, the ionization of high temperature SF(sub)6 gas, the electric and themagnetic forces and so forth mush be considered. However, in the analysis of small current interruption performance only the cold gas flow analysis needs to be carried out because the capacitive current is to small that the influence from the current can be neglected. In this paper, an empirical equation which is obtained from a series of tests to estimate the dielectric recovery strength has been applied to a real circuit breaker. The results of analysis have been compared with the test results and the reliability has been investigated.

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FSM-based Programmable Built-ln Self Test for Flash Memory (플래시 메모리를 위한 유한 상태 머신 기반의 프로그래머블 자체 테스트)

  • Kim, Ji-Hwan;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.6 s.360
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    • pp.34-41
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    • 2007
  • We popose a programmed on-line to FSM-based Programmable BIST(Buit-In Self-Test) with selected command, to select a test algorithm from a predetermined set of algorithms that are built in the Flash memory BIST. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed FSM-based Programmable BIST is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the Flash memory BIST. We also will develop a programmable Flash memory BIST generator that automatically produces Verilog code of the proposed BIST architecture for a given set of test algorithms. If experiment the proposed method, the proposed method will achieves a good flexibility with smaller circuit size compared with previous methods.

Acceleration Test of Ion Migration in FR-4 PCB Plated with Sn (Sn 표면처리된 FR-4 재질 PCB에서의 이온마이그레이션 가속시험)

  • Hwang, Soon-Mi;Jung, Young-Baek;Kim, Chul-Hee;Lee, Kwan-Hun
    • Journal of Applied Reliability
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    • v.12 no.3
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    • pp.153-163
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    • 2012
  • Recently, as a electronic components are becoming more high-density, so that electronic circuits have smaller pitches between the leads and are more vulnerable to insulation failure. And the reliability of electric insulation has become an ever important issue as device contact pitches and print patterns shrink. Ion migration occurs in highly humid environment as voltage is applied to an installed print circuit. Under highly humid and voltage applied circumstances, electronic components respond to applied voltages by electrochemical ionization of metals, and a conducting filament forms between the anode and cathode across a nonmetallic medium. This leads to short-circuit failure of the electronic component. In thesis, we study acceleration test of ion migration in FR-4 PCB plated with Sn. Voltage applied test of FR-4 PCB circuits plated with Sn was tested in the temperature and humidity environments. As a result of this test, equation of acceleration model was derived.

Solder Joints Fatigue Life of BGA Package with OSP and ENIG Surface Finish (OSP와 ENIG 표면처리에 따른 BGA 패키지의 무연솔더 접합부 피로수명)

  • Oh, Chulmin;Park, Nochang;Hong, Wonsik
    • Korean Journal of Metals and Materials
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    • v.46 no.2
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    • pp.80-87
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    • 2008
  • Many researches related to the reliability of Pb-free solder joints with PCB (printed circuit board) surface finish under thermal or vibration stresses are in progress, because the electronics is operating in hash environment. Therefore, it is necessary to assess Pb-free solder joints life with PCB surface finish under thermal and mechanical stresses. We have investigated 4-points bending fatigue lifetime of Pb-free solder joints with OSP (organic solderability preservative) and ENIG (electroless nickel and immersion gold) surface finish. To predict the bending fatigue life of Sn-3.0Ag-0.5Cu solder joints, we use the test coupons mounted 192 BGA (ball grid array) package to be added the thermal stress by conducting thermal shock test, 500, 1,000, 1,500 and 2,000 cycles, respectively. An 4-point bending test is performed in force controlling mode. It is considered that as a failure when the resistance of daisy-chain circuit of test coupons reaches more than $1,000{\Omega}$. Finally, we obtained the solder joints fatigue life with OSP and ENIG surface finish using by Weibull probability distribution.

Development of Hard-wired Instrumentation and Control for the Neutral Beam Test Facility at KAERI

  • Jung Ki-Sok;Yoon Byung-Joo;Yoon Jae-Sung;Seo Min-Seok
    • Journal of Electrical Engineering and Technology
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    • v.1 no.3
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    • pp.359-365
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    • 2006
  • Since the start of the KSTAR (Korea Superconducting Tokamak Advanced Research) project, Instrumentation and Control (I&C) of the Neutral Beam Test Facility (NB-TF) has been striving to answer diverse requests arising from various facets during the project's development and construction phases. Hard-wired electrical circuits have been designed, tested, fabricated, and finally installed to the relevant parts of the system. In relation to the vacuum system I&C, controlling functions for the rotary pumps, a Roots pump, two turbomolecular pumps, and four cryosorption pumps have been constructed. I&C for the ion source operation are the temperature and flow rate signal monitoring, Langmuir probe signal measurements, gradient grid current measurements, and arc detector circuit. For the huge power system to be monitored or safely operated, many temperature measurement functions have also been implemented for the beam line components like the neutralizer, bending magnet, ion dump, and calorimeter. Nearly all of the control and probe signals between the NB test stand and the control room were made to be transmitted through the optical cables. Failures of coolant flow or beam line vacuum pressure were made to be safely blocked from influencing the system by an appropriate interlock circuit that will shut down the extraction voltage application to the system or prevent damages to the vacuum components. Preliminary estimation of the beam power through the calorimetric measurement shows that 87.9% of the total power of the 60kV/18A beam with 200 seconds duration is absorbed by the calorimeter surface. Most of these I&C results would be highly appropriate for the construction of the main NBI facility for the KSTAR national fusion research project.

A design of radiation hardened common signal processing module for sensors in NPP (내방사선 원전센서 공통 신호처리 모듈 설계)

  • Lee, Nam-ho;Hwang, Young-gwan;Kim, Jong-yeol;Lee, Seung-min
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.6
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    • pp.1405-1410
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    • 2015
  • In this study we designed the radiation-hardened sensor signal processing modules that can be commonly used for a variety of sensors during normal operation and even in high-radiation environments caused by an accident. First development module was designed to receive the change of the R and C value from the sensors and to process the signal as a PWM modulation scheme. This module was assessed to have ± 10% error to the Full-Scale in the radiation test in the range of 12 kGy TID. The main cause of the error was analyzed as the annealing of the common circuit in the switching element and the consequent increase in the duty ratio of the pulse width modulation circuit according to the radiation dose increasement. The redesigned module for higher radiation resistivity with Stub transistor circuit was found to have less than 5% error to the Full-scale from the radiation test results for 20.7 kGy TID range.