• 한국정보통신학회논문지
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• 제13권5호
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• pp.922-930
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• 2009

유도 전동기를 전압 제어하기 위한 최적 PWM 스위칭 방법을 제시하려한다. 전압 인버터의 공간 벡터 변조 방식은 DC-버스 이용을 향상시키고 정류 손실을 감소시키기 때문에 디지털 구현의 경우 특히 선호하는 PWM 방법이다. 유도 전동기 전압 제어를 위한 최적 PWM 스위칭 방법은 제시한 최적 PWM 알고리즘을 사용하여 두 개의 활성 전압 벡터(active voltage vector)와 하나의 영 전압 벡터(zero voltage vector)로 구성하였다. 선택된 스위칭 순차 열은 변조 지수(modulation index)와 운송파(carrier wave) 주기의 함수로 정의 된다. 순차 열은 인버터 스위칭 손실과 전류 리플 값을 기준으로 사용하여 선택된다. 실험 결과 중 저 전력용으로 사용할 경우 스위칭 주파수를 증가시킴에 따라 고조파 왜곡이 감소하고 동특성이 좋아짐을 확인할 수 있었다.

• 한국통신학회논문지
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• 제16권12호
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• pp.1300-1312
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• 1991

본 논문에서는 단일버퍼 스위치에서 다중스롯호의 수용에 따른 타임스롯 순서보전을 알아보고, 타임스롯 순서보존을 고려하여 트래픽혼합비의 변화와 타임스롯의 랜덤 탐색횟수의 변화, 그리고 타임스롯의 랜덤탐색방법에 따른 호종별 호손율 톡성을 분석하였다. 이 결과는 TDX IA/B 교환기와 같은 단일 버퍼형식의 스위치망의 구성시 활용될 수 있을 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.300-312
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• 2014

A single-inductor multiple-output (SIMO) DC-DC converter providing buck and boost outputs with a new switching sequence is presented. In the proposed switching sequence, which does not require any additional blocks, input energy is delivered to outputs continuously by flowing current through the inductor, which leads to high conversion efficiency regardless of the balance between the buck and boost output loads. Furthermore, instead of multiple output loop compensation, only the freewheeling current feedback loop is compensated, which minimizes the number of off-chip components and nullifies the need for the equivalent series resistance (ESR) of the output capacitor for loop compensation. Therefore, power conversion efficiency and output voltage ripples can be improved and minimized, respectively. Implemented in a 0.35-${\mu}m$ CMOS, the proposed SIMO DC-DC converter achieves high conversion efficiency regardless of the load balance between the two outputs with maximum efficiency reaching up to 82% under heavy loads.

• 한국지능시스템학회논문지
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• 제25권2호
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• pp.139-146
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• 2015

본 논문에서는 교정 제어에 의한 스위칭 비동기 순차 머신의 모델 정합 문제를 다룬다. 스위칭 비동기 순차 머신은 스위칭 신호에 따라서 여러 개의 비동기 순차 머신 특성을 번갈아 가면서 가지는 시스템이라고 정의한다. 이번 연구에서 스위칭 시스템이 가질 수 있는 스위칭 시퀀스(sequence)는 일정하게 고정되어 있다고 가정한다. 제어 목적은 폐루프 시스템의 안정 상태 동작을 주어진 기준 모델과 일치시키는 교정 제어기의 존재조건을 규명하고 제어기를 설계하는 일이다. 이를 위해서 스위칭 비동기 머신이 가지는 도달가능성을 표현하는 새로운 skeleton 행렬을 도입하고 모델 정합 교정 제어기의 존재조건을 기술한다. 또한 사례 연구를 통해 스위칭 신호를 생성하면서 동시에 교정 제어 입력을 변화시키는 새로운 교정 제어 알고리듬을 예시한다.

• 전력전자학회논문지
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• 제27권2호
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• pp.126-133
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• 2022

This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 연구회 합동 학술발표회 논문집
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• pp.39-43
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• 1998

A large number of soft switching topologies included a resonant circuit have been proposed. But these circuits increase number of switch in circuit and complicate sequence of switching operation. In this paper, the authors propose power conversion system, DC-AC inverter of high efficiency and high power factor with soft switching mode by partial resonant method. The switching devices in a proposed circuits are operated with soft switching by the partial resonant method, that is, PRS2MPC (Partial Resonant Soft Switching Mode Power Converter). The result is that the switching loss is very low and the efficiency of system is high. And the snubber condenser used in partial resonant circuit makes charging energy regenerated at input power source for resonant operation.

• 전기전자학회논문지
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• 제7권2호
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• pp.166-171
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• 2003

본 논문은 상위 레벨 합성에서의 레지스터와 자원 할당 과정의 스위치 동작 최소화를 통한 저 전력 데이터 패스 할당 알고리즘을 제안한다. 제안하는 알고리즘은 스케줄링된 CDFG를 입력으로 할당 과정에서 전력 최소화를 수행한다. 알고리즘은 레지스터 할당과 자원 할당 과정을 나누어 수행한다. 레지스터 할당 알고리즘은 기능 장치내의 불필요한 스위칭 동작을 제거하고 멀티플렉서의 수를 최소화한다. 자원 할당 과정은 스위칭 동작을 최소화할 수 있는 연산자의 순서를 선택한다. 본 논문에서 제안하는 알고리즘과 genesis-lp 상위 레벨 합성시스템을 벤치마크를 이용한 비교 실험결과 평균 15.3%의 전력 감소효과가 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 B
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• pp.1148-1150
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• 2003

Power conversion system must be increased switching frequency in order to achieve a small size, a light weight and a low noise. However, the switches of converter are subjected to high switching power losses and switching stresses. As a result of those, the power system brings on a low efficiency. To improved these, a large number of soft switching topologies included a resonant circuit has been prosed. But these circuits increase number of switch in circuit and complicate sequence of switching operation. In this paper, the authors propose a high power factor and high efficiency DC-DC converter using single-pulse soft switching by partial resonant switching node. The switching devices in a prosed circuit are operated with soft switching by the partial resonant method, that is, Partial Resonant Switch Mode Power Converter. The partial resonant circuit makes use of a inductor using step up and a condenser of loss-less snubber. The result is that the switching loss is very low and the efficiency of system is high. Also the proposed converter is deemed the most suitable for high power applications where the power switching devices are used. Some simulative results on computer results are included to confirm the validity of the analytical results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.121-124
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• 2001

This paper proposed resource allocation algorithm for the minimum switching activity of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. The resource allocation method after scheduling use the power function calculating average hamming distance and switching activity of the between two input. First of all, the switching activity is calculated by the input value after calculating the average hamming distance between operation. In this paper, the proposed method though high If level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and max control step. And it is the reduction effect from 6% to 8%.

• Journal of Power Electronics
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• 제18권6호
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• pp.1729-1750
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• 2018

Voltage source inverters (VSIs) are widely used to drive induction motors in industry applications. The quality of output waveforms depends on the switching sequences used in pulse width modulation (PWM). In this work, all existing optimal space vector pulse width modulation (SVPWM) switching strategies are studied. The performance of existing SVPWM switching strategies is optimized to realize a tradeoff between quality of output waveforms and switching losses. This study generalizes the existing optimal switching sequences for total harmonic distortions (THDs) and switching losses for different modulation indexes and reference angles with a parameter called quality factor. This factor provides a common platform in which the THDs and switching losses of different SVPWM techniques can be compared. The optimal spatial distribution of each sequence is derived on the basis of the quality factor to minimize harmonic current distortions and switching losses in a sector; the result is the minimum ripple loss SVPWM (MRSLPWM). By employing the sequences from optimized switching maps, the proposed method can simultaneously reduce THDs and switching losses. Two hybrid SVPWM techniques are proposed to reduce line current distortions and switching losses in motor drives. The proposed hybrid SVPWM strategies are MRSLPWM 30 and MRSLPWM 90. With a low-cost PIC microcontroller (PIC18F452), the proposed hybrid SVPWM techniques and the quality of output waveforms are experimentally validated on a 2 kVA VSI based on a three-phase two-level insulated gate bipolar transistor.