• Journal of the Korea Computer Industry Society
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• v.4 no.12
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• pp.1043-1052
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• 2003

In this paper, we present a fast motion estimation algorithm to reduce the computations of block matching algorithm for motion estimation in video coding. The proposed algorithm is based on Multi-level Successive Elimination Algorithm and Efficient Multi-level Successive Elimination Algorithms. The best estimate of the motion vectors can be obtained by hierarchical search point sampling and thus the proposed algorithm can decrease the number of matching evaluations that require very intensive computations. The efficiency of the proposed algorithm was verified by experimental results.

• Communications for Statistical Applications and Methods
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• v.26 no.2
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• pp.175-189
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• 2019

The problem of the estimation of quantitative sensitive variable using the item sum technique (IST) on successive occasions has been discussed. IST difference, IST regression, and IST general class of estimators have been proposed to estimate quantitative sensitive variable at the current occasion in two occasion successive sampling. The proposed new estimators have been elaborated under Trappmann et al. (Journal of Survey Statistics and Methodology, 2, 58-77, 2014) as well as Perri et al. (Biometrical Journal, 60, 155-173, 2018) allocation designs to allocate long list and short list samples of IST. The properties of all proposed estimators have been derived including optimum replacement policy. The proposed estimators have been mutually compared under the above mentioned allocation designs. The comparison has also been conducted with a direct method. Numerical applications through empirical as well as simplistic simulation has been used to show how the illustrated IST on successive occasions may venture in practical situations.

• Communications for Statistical Applications and Methods
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• v.24 no.3
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• pp.255-269
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• 2017

This article explores the analysis of longitudinal surveys in which same units are investigated on several occasions. Multivariate exponential ratio type estimator has been proposed for the estimation of the finite population median at the current occasion in two occasion longitudinal surveys. Information on several additional auxiliary variables, which are stable over time and readily available on both the occasions, has been utilized. Properties of the proposed multivariate estimator, including the optimum replacement strategy, are presented. The proposed multivariate estimator is compared with the sample median estimator when there is no matching from a previous occasion and with the exponential ratio type estimator in successive sampling when information is available on only one additional auxiliary variable. The merits of the proposed estimator are justified by empirical interpretations and validated by a simulation study with the help of some natural populations.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• The Korean Journal of Applied Statistics
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• v.27 no.4
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• pp.513-521
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• 2014

If the target error of an estimator at the present time is greater than the coefficient of variation(CV) of the estimator at the previous time, sample size at this point should be decreased. Various papers have researched sample size determination methods using the CV of an estimator at the previous time, variation of population size and target error of the estimator at this time in sampling on successive occasions. We research a new sample size determination method additionally using change of population CV. We compare the proposed method with existing ones in various simulation settings.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.47-50
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• 2002

An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.26 no.4
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• pp.369-379
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• 1993

Using a successive removal approach the mechanism of sampling capture efficiency of blue crabs by dredges was studied in Chesapeake Bay during winter 1992. For the twenty-six field experiments no significant statistical differences were detected in dredge efficiency using general linear model analysis by factors including bottom sediments, water depths, and sampling vessels. Dredge efficiency (i.e., catchability) was estimated by two methods, Leslie (Leslie and Davis, 1939) and a simple revised method. Mean catchability was estimated at 0.26 (SE=0.03), indicating that only $26\%$($95\%\;C. I.=20{\sim}32\%$) of crabs present in the path of the dredge of a given sampling area are caught with a single dredge tow. Dredge efficiency declined exponentially as crab density increased.

• Structural Engineering and Mechanics
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• v.82 no.2
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• pp.245-258
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• 2022

Many Structural Health Monitoring (SHM) methods have been proposed for structural damage diagnosis and prognosis. However, SHM for pinched hysteretic structures can be problematic due to the high level of nonlinearity. The model-free hysteresis loop analysis (HLA) has displayed notable robustness and accuracy in identifying damage for full-scaled and scaled test buildings. In this paper, the performance of HLA is compared with seven other SHM methods in identifying lateral elastic stiffness for a six-story numerical building with highly nonlinear pinching behavior. Two successive earthquakes are employed to compare the accuracy and consistency of methods within and between events. Robustness is assessed across sampling rates 50-1000 Hz in noise-free condition and then assessed with 10% root mean square (RMS) noise added to responses at 250 Hz sampling rate. Results confirm HLA is the most robust method to sampling rate and noise. HLA preserves high accuracy even when the sampling rate drops to 50 Hz, where the performance of other methods deteriorates considerably. In noisy conditions, the maximum absolute estimation error is less than 4% for HLA. The overall results show HLA has high robustness and accuracy for an extremely nonlinear, but realistic case compared to a range of leading and recent model-based and model-free methods.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.