• 제목/요약/키워드: subthreshold region design

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InGaAs-based Tunneling Field-effect Transistor with Stacked Dual-metal Gate with PNPN Structure for High Performance

  • Kwon, Ra Hee;Lee, Sang Hyuk;Yoon, Young Jun;Seo, Jae Hwa;Jang, Young In;Cho, Min Su;Kim, Bo Gyeong;Lee, Jung-Hee;Kang, In Man
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권2호
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    • pp.230-238
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    • 2017
  • We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.