• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.3
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• pp.397-404
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• 2011

In this research, wish to suggest method to embody system that can accommodate defect of PLC and find actual propriety. Defect permission control system minimizes production damage because enables repair and checking without discontinuance and improve believability about whole system. Propose duplexing of system to embody this fault tolerant system. Therefore, composed control system that can permit defect or breakdown duplexings of various module proposing this system, and confirms to simulation and actuality kiln of defect permission control system through an application experiment, and compares for mean time between defect by estimate and defect special quality and system configuration of failure(failure) to improve believability of PLC control system together. In proposed system expression method and system mode and relation with operation mode, error discovery mode and switching tube of duplexing mode, and PLC's central processing unit of node study algorithm about master-standby conversion driving and continuous operation of 2 channels method that have 2 that is not one and deduced continuous operation method and result about defect permission in this algorithm and applies this result to actuality kiln control system and confirms continuous operation about PLC defect permission.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.376-383
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• 2022

The improved performance of computer parts, such as graphic card, CPU, and main board, has led to the need for power supplies with a high power output. The dynamic load profile rapidly changes the usage of power consumption depending on load operations, such as PC power and air conditioner. Under dynamic load profile conditions, power consumption can be classified into maximum, normal, and standby power. Several problems arise in the case of maximum power. Peak power is generated at the system power source in the maximum-power situation. Frequent generation of peak power can cause high-frequency problems and reduce the life of high-pressure parts (especially high-pressure capacitors). For example, when a plurality of PCs are used, system overload occurs due to peak power generation and causes problems, such as power failure and increase in electricity bills due to exceeded contract power. To solve this problem, a system peak power limit/compensation power circuit is proposed for a power supply under dynamic load profile conditions. The proposed circuit detects the system current to determine the power situation of the load. When the system current is higher than the set level, the circuit recognizes that the system current generates peak power and compensates for the load power through a converter using a super capacitor as the power source. Thus, the peak power of loads with a dynamic load profile is limited and compensated for, and problems, such as high-frequency issues, are solved. In addition, the life of high-pressure parts is increased.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.293-303
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• 2008

As the computing environment moves to the wireless and handheld system, the power efficiency is getting more important. That is the case especially in the embedded hand-held system and the power consumed by the memory system takes the second largest portion in overall. To save energy consumed in the memory system we can utilize low power mode of SDRAM. In the case of RDRAM, nap mode consumes less than 5% of the power consumed in active or standby mode. However hardware controller itself can't use this facility efficiently unless the operating system cooperates. In this paper we focus on how to minimize the number of active units of SDRAM. The operating system allocates its physical pages so that only a few units of SDRAM need to be activated and the unnecessary SDRAM can be put into nap mode. This work can be considered as a generalized and system-wide version of PAVM(Power-Aware Virtual Memory) research. We take all the physical memory into account, especially buffer cache, which takes an half of total memory usage on average. Because of the portion of buffer cache and its importance, PAVM approach cannot be robust without taking the buffer cache into account. In this paper, we analyze the RAM usage and propose power-aware page allocation policy. Especially the pages mapped into the process' address space and the buffer cache pages are considered. The relationship and interactions of these two kinds of pages are analyzed and exploited for energy saving.