• Journal of KIISE:Databases
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• v.30 no.6
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• pp.651-665
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• 2003

To reduce cache misses emerges as the most important issue in today's situation of main memory databases, in which CPU speeds have been increasing at 60% per year, and memory speeds at 10% per year. Recent researches have demonstrated that cache-conscious index structure such as the CR-tree outperforms the R-tree variants. Its search performance can be poor than the original R-tree, however, since it uses a lossy compression scheme. In this paper, we propose alternatively a cache-conscious version of the R-tree, which we call MR-tree. The MR-tree propagates node splits upward only if one of the internal nodes on the insertion path has empty room. Thus, the internal nodes of the MR-tree are almost 100% full. In case there is no empty room on the insertion path, a newly-created leaf simply becomes a child of the split leaf. The height of the MR-tree increases according to the sequence of inserting objects. Thus, the HeightBalance algorithm is executed when unbalanced heights of child nodes are detected. Additionally, we also propose the CCMR-tree in order to build a more cache-conscious MR-tree. Our experimental and analytical study shows that the two-dimensional MR-tree performs search up to 2.4times faster than the ordinary R-tree while maintaining slightly better update performance and using similar memory space.

• Journal of KIISE:Databases
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• v.35 no.1
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• pp.17-28
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• 2008

Recently, main memory access is a performance bottleneck for many computer applications. Cache memory is introduced in order to reduce memory access latency. However, it is possible for cache memory to reduce memory access latency, when desired data are located on cache. EST tree is proposed to solve this problem by improving T tree. However, when doing a range search, EST tree has to search unnecessary nodes. Therefore, this paper proposes $CST^+$ tree which has the merit of CST tree and is possible to do a range search by linking data nodes with linked lists. By experiments, we show that $CST^+$ is $4{\sim}10$ times as fast as CST and $CSB^+$. In addition, rebuilding an index Is an essential step for the database recovery from system failure. In this paper, we propose a fast tree index rebuilding algorithm called MaxPL. MaxPL has no node-split overhead and employs a parallelism for reading the data records and inserting the keys into the index. We show that MaxPL is $2{\sim}11$ times as fast as sequential insert and batch insert.

• Proceedings of the Korea Contents Association Conference
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• 2004.05a
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• pp.234-240
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• 2004

Now that the e-commerce users are explosively increasing, there is always followed by a sharp increase in load from the e-commerce system and the heavy traffic on the network, where leads to the delayed service for the client's request. The natural consequences contain decreasing customer satisfaction and weakening the business's competitive position in markets. Therefore, we'll need to study the e-commerce system in due consideration of the operational efficiency and response speed. This study includes a design of e-commerce system, with a hierarchical structure based on the local server, which has the capability of caching necessary to distribute the system load, makes a proposal concerning a split web-cache algorithm devoted to the local web server to finally give an analysis of the performance through the appropriate trial.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.24-32
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• 1998

The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.